4  * (C) Copyright 2012-2014
7  * SPDX-License-Identifier:     GPL-2.0+
47 		if (!(pllctl_reg_read(data->pll, stat) & PLLSTAT_GOSTAT_MASK))  in wait_for_completion()
54 	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC_MASK |  in bypass_main_pll()
65 	pllm = data->pll_m - 1;  in configure_mult_div()
66 	plld = (data->pll_d - 1) & CFG_PLLCTL0_PLLD_MASK;  in configure_mult_div()
69 	if (data->pll == MAIN_PLL)  in configure_mult_div()
70 		pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);  in configure_mult_div()
72 	clrsetbits_le32(keystone_pll_regs[data->pll].reg0,  in configure_mult_div()
77 	bwadj = (data->pll_m - 1) >> 1; /* Divide pllm by 2 */  in configure_mult_div()
78 	clrsetbits_le32(keystone_pll_regs[data->pll].reg0,  in configure_mult_div()
83 	clrsetbits_le32(keystone_pll_regs[data->pll].reg1,  in configure_mult_div()
87 	clrsetbits_le32(keystone_pll_regs[data->pll].reg0,  in configure_mult_div()
96 	pllod = data->pll_od - 1;  in configure_main_pll()
101 	tmp = pllctl_reg_read(data->pll, secctl);  in configure_main_pll()
105 		setbits_le32(keystone_pll_regs[data->pll].reg1,  in configure_main_pll()
111 		pllctl_reg_setbits(data->pll, secctl, SECCTL_BYPASS_MASK);  in configure_main_pll()
112 		pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK);  in configure_main_pll()
116 		pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK);  in configure_main_pll()
124 	pllctl_reg_rmw(data->pll, secctl, SECCTL_OP_DIV_MASK,  in configure_main_pll()
131 			offset = pllctl_reg(data->pll, div1) + i;  in configure_main_pll()
133 			offset = pllctl_reg(data->pll, div4) + (i - 3);  in configure_main_pll()
135 		if (divn_val[i] != -1) {  in configure_main_pll()
142 		pllctl_reg_setbits(data->pll, alnctl, alnctl_val);  in configure_main_pll()
147 		pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GOSTAT_MASK);  in configure_main_pll()
152 	pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST_MASK);  in configure_main_pll()
154 	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST_MASK);  in configure_main_pll()
158 	pllctl_reg_clrbits(data->pll, secctl, SECCTL_BYPASS_MASK);  in configure_main_pll()
159 	pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN_MASK);  in configure_main_pll()
164 	int pllod = data->pll_od - 1;  in configure_secondary_pll()
167 	if (cpu_is_k2hk() && data->pll == TETRIS_PLL)  in configure_secondary_pll()
171 	setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_ENSAT_MASK);  in configure_secondary_pll()
172 	setbits_le32(keystone_pll_regs[data->pll].reg0,  in configure_secondary_pll()
178 	clrsetbits_le32(keystone_pll_regs[data->pll].reg0,  in configure_secondary_pll()
184 	setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK);  in configure_secondary_pll()
189 	if (data->pll == PASS_PLL && cpu_is_k2hk())  in configure_secondary_pll()
192 	clrbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK);  in configure_secondary_pll()
196 	/* Switch to PLL mode */  in configure_secondary_pll()
197 	clrbits_le32(keystone_pll_regs[data->pll].reg0,  in configure_secondary_pll()
201 	if (cpu_is_k2hk() && data->pll == TETRIS_PLL)  in configure_secondary_pll()
207 	if (data->pll == MAIN_PLL)  in init_pll()
236 	for (speed = DEVSPEED_NUMSPDS; speed >= 0; speed--) {  in get_max_speed()
277  * pll_freq_get - get pll frequency
303 		switch (pll) {  in pll_freq_get()
346 	unsigned long freq = 0;  in ks_clk_get_rate()  local
348 	switch (clk) {  in ks_clk_get_rate()
350 		freq = pll_freq_get(CORE_PLL);  in ks_clk_get_rate()
353 		freq = pll_freq_get(PASS_PLL);  in ks_clk_get_rate()
357 			freq = pll_freq_get(TETRIS_PLL);  in ks_clk_get_rate()
360 		freq = pll_freq_get(DDR3A_PLL);  in ks_clk_get_rate()
364 			freq = pll_freq_get(DDR3B_PLL);  in ks_clk_get_rate()
368 			freq = pll_freq_get(UART_PLL);  in ks_clk_get_rate()
372 		freq = pll_freq_get(CORE_PLL) / pll0div_read(1);  in ks_clk_get_rate()
378 		freq = pll_freq_get(CORE_PLL) / pll0div_read(3);  in ks_clk_get_rate()
381 		freq = pll_freq_get(CORE_PLL) / pll0div_read(4);  in ks_clk_get_rate()
384 		freq = ks_clk_get_rate(sys_clk0_clk) / 2;  in ks_clk_get_rate()
387 		freq = ks_clk_get_rate(sys_clk0_clk) / 3;  in ks_clk_get_rate()
390 		freq = ks_clk_get_rate(sys_clk0_clk) / 4;  in ks_clk_get_rate()
393 		freq = ks_clk_get_rate(sys_clk0_clk) / 6;  in ks_clk_get_rate()
396 		freq = ks_clk_get_rate(sys_clk0_clk) / 8;  in ks_clk_get_rate()
399 		freq = ks_clk_get_rate(sys_clk0_clk) / 12;  in ks_clk_get_rate()
402 		freq = ks_clk_get_rate(sys_clk0_clk) / 24;  in ks_clk_get_rate()
405 		freq = ks_clk_get_rate(sys_clk1_clk) / 3;  in ks_clk_get_rate()
408 		freq = ks_clk_get_rate(sys_clk1_clk) / 4;  in ks_clk_get_rate()
411 		freq = ks_clk_get_rate(sys_clk1_clk) / 6;  in ks_clk_get_rate()
414 		freq = ks_clk_get_rate(sys_clk1_clk) / 12;  in ks_clk_get_rate()
420 	return freq;  in ks_clk_get_rate()