2  * Keystone2: pll initialization
4  * (C) Copyright 2012-2014
7  * SPDX-License-Identifier:     GPL-2.0+
47 		if (!(pllctl_reg_read(data->pll, stat) & PLLSTAT_GOSTAT_MASK))  in wait_for_completion()
54 	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC_MASK |  in bypass_main_pll()
65 	pllm = data->pll_m - 1;  in configure_mult_div()
66 	plld = (data->pll_d - 1) & CFG_PLLCTL0_PLLD_MASK;  in configure_mult_div()
69 	if (data->pll == MAIN_PLL)  in configure_mult_div()
70 		pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);  in configure_mult_div()
72 	clrsetbits_le32(keystone_pll_regs[data->pll].reg0,  in configure_mult_div()
77 	bwadj = (data->pll_m - 1) >> 1; /* Divide pllm by 2 */  in configure_mult_div()
78 	clrsetbits_le32(keystone_pll_regs[data->pll].reg0,  in configure_mult_div()
83 	clrsetbits_le32(keystone_pll_regs[data->pll].reg1,  in configure_mult_div()
87 	clrsetbits_le32(keystone_pll_regs[data->pll].reg0,  in configure_mult_div()
96 	pllod = data->pll_od - 1;  in configure_main_pll()
101 	tmp = pllctl_reg_read(data->pll, secctl);  in configure_main_pll()
105 		setbits_le32(keystone_pll_regs[data->pll].reg1,  in configure_main_pll()
110 		/* Powerdown and powerup Main Pll */  in configure_main_pll()
111 		pllctl_reg_setbits(data->pll, secctl, SECCTL_BYPASS_MASK);  in configure_main_pll()
112 		pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK);  in configure_main_pll()
116 		pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK);  in configure_main_pll()
124 	pllctl_reg_rmw(data->pll, secctl, SECCTL_OP_DIV_MASK,  in configure_main_pll()
131 			offset = pllctl_reg(data->pll, div1) + i;  in configure_main_pll()
133 			offset = pllctl_reg(data->pll, div4) + (i - 3);  in configure_main_pll()
135 		if (divn_val[i] != -1) {  in configure_main_pll()
142 		pllctl_reg_setbits(data->pll, alnctl, alnctl_val);  in configure_main_pll()
147 		pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GOSTAT_MASK);  in configure_main_pll()
151 	/* Reset PLL */  in configure_main_pll()
152 	pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST_MASK);  in configure_main_pll()
154 	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST_MASK);  in configure_main_pll()
155 	sdelay(105000);	/* Wait for PLL Lock time (min 50 us) */  in configure_main_pll()
157 	/* Enable PLL */  in configure_main_pll()
158 	pllctl_reg_clrbits(data->pll, secctl, SECCTL_BYPASS_MASK);  in configure_main_pll()
159 	pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN_MASK);  in configure_main_pll()
164 	int pllod = data->pll_od - 1;  in configure_secondary_pll()
166 	/* Enable Glitch free bypass for ARM PLL */  in configure_secondary_pll()
167 	if (cpu_is_k2hk() && data->pll == TETRIS_PLL)  in configure_secondary_pll()
171 	setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_ENSAT_MASK);  in configure_secondary_pll()
172 	setbits_le32(keystone_pll_regs[data->pll].reg0,  in configure_secondary_pll()
178 	clrsetbits_le32(keystone_pll_regs[data->pll].reg0,  in configure_secondary_pll()
183 	/* Reset PLL */  in configure_secondary_pll()
184 	setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK);  in configure_secondary_pll()
188 	/* Select the Output of PASS PLL as input to PASS */  in configure_secondary_pll()
189 	if (data->pll == PASS_PLL && cpu_is_k2hk())  in configure_secondary_pll()
192 	clrbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK);  in configure_secondary_pll()
193 	/* Wait for 500 * REFCLK cucles * (PLLD + 1) */  in configure_secondary_pll()
196 	/* Switch to PLL mode */  in configure_secondary_pll()
197 	clrbits_le32(keystone_pll_regs[data->pll].reg0,  in configure_secondary_pll()
200 	/* Select the Output of ARM PLL as input to ARM */  in configure_secondary_pll()
201 	if (cpu_is_k2hk() && data->pll == TETRIS_PLL)  in configure_secondary_pll()
207 	if (data->pll == MAIN_PLL)  in init_pll()
222 	int pll;  in init_plls()  local
224 	for (pll = MAIN_PLL; pll < MAX_PLL_COUNT; pll++) {  in init_plls()
225 		data = get_pll_init_data(pll);  in init_plls()
236 	for (speed = DEVSPEED_NUMSPDS; speed >= 0; speed--) {  in get_max_speed()
250 	if (cpu_is_k2hk() && (cpu_revision() <= 1))  in read_efuse_bootrom()
277  * pll_freq_get - get pll frequency
278  * @pll:	pll identifier
280 static unsigned long pll_freq_get(int pll)  in pll_freq_get()  argument
282 	unsigned long mult = 1, prediv = 1, output_div = 2;  in pll_freq_get()
286 	if (pll == MAIN_PLL) {  in pll_freq_get()
288 		if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN_MASK) {  in pll_freq_get()
289 			/* PLL mode */  in pll_freq_get()
291 			prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1;  in pll_freq_get()
294 				(pllctl_reg_read(pll, mult) &  in pll_freq_get()
295 				 PLLM_MULT_LO_MASK)) + 1;  in pll_freq_get()
296 			output_div = ((pllctl_reg_read(pll, secctl) &  in pll_freq_get()
298 				       SECCTL_OP_DIV_SHIFT) + 1;  in pll_freq_get()
303 		switch (pll) {  in pll_freq_get()
332 			prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1;  in pll_freq_get()
334 				CFG_PLLCTL0_PLLM_SHIFT) + 1;  in pll_freq_get()
336 				      CFG_PLLCTL0_CLKOD_SHIFT) + 1;  in pll_freq_get()
372 		freq = pll_freq_get(CORE_PLL) / pll0div_read(1);  in ks_clk_get_rate()