25 		reg = readl(&scg1_regs->sosccsr);  in scg_src_get_rate()
31 		reg = readl(&scg1_regs->firccsr);  in scg_src_get_rate()
37 		reg = readl(&scg1_regs->sirccsr);  in scg_src_get_rate()
43 		reg = readl(&scg1_regs->rtccsr);  in scg_src_get_rate()
77 	reg = readl(&scg1_regs->sirccsr);  in scg_sircdiv_get_rate()
81 	reg = readl(&scg1_regs->sircdiv);  in scg_sircdiv_get_rate()
115 	reg = readl(&scg1_regs->firccsr);  in scg_fircdiv_get_rate()
119 	reg = readl(&scg1_regs->fircdiv);  in scg_fircdiv_get_rate()
153 	reg = readl(&scg1_regs->sosccsr);  in scg_soscdiv_get_rate()
157 	reg = readl(&scg1_regs->soscdiv);  in scg_soscdiv_get_rate()
203 	reg = readl(&scg1_regs->apllpfd);  in scg_apll_pfd_get_rate()
253 	reg = readl(&scg1_regs->spllpfd);  in scg_spll_pfd_get_rate()
273 	reg = readl(&scg1_regs->apllcfg);  in scg_apll_get_rate()
301 	reg = readl(&scg1_regs->spllcfg);  in scg_spll_get_rate()
336 	reg = readl(&scg1_regs->ddrccr);  in scg_ddr_get_rate()
344 		reg = readl(&scg1_regs->apllcfg);  in scg_ddr_get_rate()
361 	reg = readl(&scg1_regs->niccsr);  in scg_nic_get_rate()
436 	reg = readl(&scg1_regs->csr);  in scg_sys_get_rate()
483 		reg = readl(&scg1_regs->spllcsr);  in decode_pll()
488 		reg = readl(&scg1_regs->spllcfg);  in decode_pll()
504 		num = readl(&scg1_regs->spllnum);  in decode_pll()
505 		denom = readl(&scg1_regs->splldenom);  in decode_pll()
512 		reg = readl(&scg1_regs->apllcsr);  in decode_pll()
517 		reg = readl(&scg1_regs->apllcfg);  in decode_pll()
533 		num = readl(&scg1_regs->apllnum);  in decode_pll()
534 		denom = readl(&scg1_regs->aplldenom);  in decode_pll()
541 		reg = readl(&scg1_regs->upllcsr);  in decode_pll()
681 	reg = readl(addr);  in scg_enable_pll_pfd()
699 		reg = readl(addr);  in scg_enable_pll_pfd()
719 	reg = readl(SIM0_RBASE + 0x3C);  in scg_enable_usb_pll()
726 	if (!(readl(&usbphy->usb1_pll_480_ctrl) & PLL_USB_LOCK_MASK)) {  in scg_enable_usb_pll()
759 			if (readl(&usbphy->usb1_pll_480_ctrl) &  in scg_enable_usb_pll()
781 			if (readl(&scg1_regs->upllcsr) &  in scg_enable_usb_pll()
787 			reg = readl(SIM0_RBASE + 0x3C);  in scg_enable_usb_pll()
813 	rccr_reg_val = readl(&scg1_regs->rccr);  in scg_a7_rccr_init()
855 	val = readl(&scg1_regs->spllcsr);  in scg_a7_spll_init()
869 	val = readl(&scg1_regs->spllpfd);  in scg_a7_spll_init()
882 	val = readl(&scg1_regs->spllcsr);  in scg_a7_spll_init()
887 	while (!(readl(&scg1_regs->spllcsr) & SCG_SPLL_CSR_SPLLVLD_MASK))  in scg_a7_spll_init()
891 	val = readl(&scg1_regs->spllpfd);  in scg_a7_spll_init()
897 	val = readl(&scg1_regs->spllpfd);  in scg_a7_spll_init()
902 	while (!(readl(&scg1_regs->spllpfd) & SCG_PLL_PFD0_VALID_MASK))  in scg_a7_spll_init()
964 	val = readl(&scg1_regs->apllcsr);  in scg_a7_apll_init()
969 	val = readl(&scg1_regs->apllpfd);  in scg_a7_apll_init()
978 	val = readl(&scg1_regs->apllcsr);  in scg_a7_apll_init()
983 	while (!(readl(&scg1_regs->apllcsr) & SCG_APLL_CSR_APLLVLD_MASK))  in scg_a7_apll_init()
987 	val = readl(&scg1_regs->apllpfd);  in scg_a7_apll_init()
993 	val = readl(&scg1_regs->apllpfd);  in scg_a7_apll_init()
998 	while (!(readl(&scg1_regs->apllpfd) & SCG_PLL_PFD0_VALID_MASK))  in scg_a7_apll_init()
1013 	while (!(readl(&scg1_regs->firccsr) & SCG_FIRC_CSR_FIRCVLD_MASK))  in scg_a7_firc_init()
1055 	while (!(readl(&scg1_regs->sosccsr) & SCG_SOSC_CSR_SOSCVLD_MASK))  in scg_a7_soscdiv_init()
1078 	rccr_reg_val = readl(&scg1_regs->rccr);  in scg_a7_sys_clk_sel()
1086 	debug("SCG Version: 0x%x\n", readl(&scg1_regs->verid));  in scg_a7_info()
1087 	debug("SCG Parameter: 0x%x\n", readl(&scg1_regs->param));  in scg_a7_info()
1088 	debug("SCG RCCR Value: 0x%x\n", readl(&scg1_regs->rccr));  in scg_a7_info()
1089 	debug("SCG Clock Status: 0x%x\n", readl(&scg1_regs->csr));  in scg_a7_info()