Lines Matching full:spll
318 clk_debug("scg_spll_get_rate SPLL %u\n", rate); in scg_spll_get_rate()
798 /* A7 domain system clock source is SPLL */
801 /* A7 Core clck = SPLL PFD0 / 1 = 500MHz / 1 = 500MHz */
833 /* SPLL output clocks (including PFD outputs) selected */
835 /* SPLL PFD output clock selected */
847 /*413Mhz = A7 SPLL(528MHz) * 18/23 */
868 /* Gate off A7 SPLL PFD0 ~ PDF4 */ in scg_a7_spll_init()
876 /* ================ A7 SPLL Configuration Start ============== */ in scg_a7_spll_init()
886 /* Wait for A7 SPLL clock ready */ in scg_a7_spll_init()
890 /* Configure A7 SPLL PFD0 */ in scg_a7_spll_init()
896 /* Un-gate A7 SPLL PFD0 */ in scg_a7_spll_init()
901 /* Wait for A7 SPLL PFD0 clock being valid */ in scg_a7_spll_init()
905 /* ================ A7 SPLL Configuration End ============== */ in scg_a7_spll_init()