Lines Matching full:firc

1002 /* SCG1(A7) FIRC DIV configurations */
1003 /* Disable FIRC DIV3 */
1005 /* FIRC DIV2 = 48MHz / 1 = 48MHz */
1007 /* Disable FIRC DIV1 */
1012 	/* Wait for FIRC clock ready */  in scg_a7_firc_init()
1016 	/* Configure A7 FIRC DIV1 ~ DIV3 */  in scg_a7_firc_init()
1044 /* SCG1(A7) FIRC DIV configurations */
1045 /* Enable FIRC DIV3 */
1047 /* FIRC DIV2 = 48MHz / 1 = 48MHz */
1049 /* Enable FIRC DIV1 */
1054 	/* Wait for FIRC clock ready */  in scg_a7_soscdiv_init()
1058 	/* Configure A7 FIRC DIV1 ~ DIV3 */  in scg_a7_soscdiv_init()