Lines Matching full:pfd

288 		/* APLL PFD clock */  in scg_apll_get_rate()
321 		/* APLL PFD clock */  in scg_spll_get_rate()
326 		clk_debug("scg_spll_get_rate PFD %u\n", rate);  in scg_spll_get_rate()
680 	/* Gate the PFD */  in scg_enable_pll_pfd()
691 	 * Un-gate the PFD  in scg_enable_pll_pfd()
697 	/* Wait for PFD clock being valid */  in scg_enable_pll_pfd()
833 /* SPLL output clocks (including PFD outputs) selected */
835 /* SPLL PFD output clock selected */
861 	 * "When changing PFD values, it is recommneded PFDx clock  in scg_a7_spll_init()
863 	 * then program the new PFD value, then poll the PFDx_VALID  in scg_a7_spll_init()
934 /* APLL output clocks (including PFD outputs) selected	<<2 */
936 /* APLL PFD output clock selected <<1 */