4  * SPDX-License-Identifier:	GPL-2.0+
9 #include <asm/arch/imx-regs.h>
12 #include <asm/mach-imx/boot_mode.h>
13 #include <asm/mach-imx/dma.h>
14 #include <asm/mach-imx/hab.h>
15 #include <asm/mach-imx/rdc-sema.h>
16 #include <asm/arch/imx-rdc.h>
39  * at A7 core side. At default, all resources are in domain 0 - 3.
102  * defines a 2-bit SPEED_GRADING
113 	struct fuse_bank *bank = &ocotp->bank[1];  in get_cpu_speed_grade_hz()
115 		(struct fuse_bank1_regs *)bank->fuse_regs;  in get_cpu_speed_grade_hz()
118 	val = readl(&fuse->tester3);  in get_cpu_speed_grade_hz()
137  * defines a 2-bit SPEED_GRADING
144 	struct fuse_bank *bank = &ocotp->bank[1];  in get_cpu_temp_grade()
146 		(struct fuse_bank1_regs *)bank->fuse_regs;  in get_cpu_temp_grade()
149 	val = readl(&fuse->tester3);  in get_cpu_temp_grade()
155 			*minc = -40;  in get_cpu_temp_grade()
158 			*minc = -40;  in get_cpu_temp_grade()
161 			*minc = -20;  in get_cpu_temp_grade()
174 	struct fuse_bank *bank = &ocotp->bank[1];  in is_mx7d()
176 		(struct fuse_bank1_regs *)bank->fuse_regs;  in is_mx7d()
179 	val = readl(&fuse->tester4);  in is_mx7d()
190 	u32 reg = readl(&ccm_anatop->digprog);  in get_cpu_rev()
221 	 * The management data input/output (MDIO) requires open-drain,  in imx_enet_mdio_fixup()
228 		setbits_le32(&gpr_regs->gpr[0],  in imx_enet_mdio_fixup()
260 		env_set("soc", "imx7d");  in arch_misc_init()
273 	struct fuse_bank *bank = &ocotp->bank[0];  in get_board_serial()
275 		(struct fuse_bank0_regs *)bank->fuse_regs;  in get_board_serial()
277 	serialnr->low = fuse->tester0;  in get_board_serial()
278 	serialnr->high = fuse->tester1;  in get_board_serial()
286 	struct fuse_bank *bank = &ocotp->bank[9];  in imx_get_mac_from_fuse()
288 		(struct fuse_bank9_regs *)bank->fuse_regs;  in imx_get_mac_from_fuse()
291 		u32 value = readl(&fuse->mac_addr1);  in imx_get_mac_from_fuse()
295 		value = readl(&fuse->mac_addr0);  in imx_get_mac_from_fuse()
301 		u32 value = readl(&fuse->mac_addr2);  in imx_get_mac_from_fuse()
307 		value = readl(&fuse->mac_addr1);  in imx_get_mac_from_fuse()
318 	struct src *src_reg = (struct src *)SRC_BASE_ADDR;  in arch_auxiliary_core_up()
331 	clrsetbits_le32(&src_reg->m4rcr, SRC_M4RCR_M4C_NON_SCLR_RST_MASK,  in arch_auxiliary_core_up()
340 	struct src *src_reg = (struct src *)SRC_BASE_ADDR;  in arch_auxiliary_core_check_up()
342 	val = readl(&src_reg->m4rcr);  in arch_auxiliary_core_check_up()
352 	u32 reg = readw(&wdog->wcr);  in set_wdog_reset()
358 	reg = readw(&wdog->wcr);  in set_wdog_reset()
361 	 * WDZST bit is write-once only bit. Align this bit in kernel,  in set_wdog_reset()
365 	writew(reg, &wdog->wcr);  in set_wdog_reset()
398 	u8 boot_type = (*p)->boot_dev_type;  in get_boot_device()
399 	u8 boot_instance = (*p)->boot_dev_instance;  in get_boot_device()
437 	int devno = (*p)->boot_dev_instance;  in mmc_get_env_dev()
438 	u8 boot_type = (*p)->boot_dev_type;  in mmc_get_env_dev()