79 	u32 target;  in enable_usboh3_clk()  local
86 		target = CLK_ROOT_ON |  in enable_usboh3_clk()
90 		clock_set_target_val(USB_HSIC_CLK_ROOT, target);  in enable_usboh3_clk()
527 	u32 target;  in enable_i2c_clk()  local
537 		target = CLK_ROOT_ON |  in enable_i2c_clk()
541 		clock_set_target_val(I2C1_CLK_ROOT + i2c_num, target);  in enable_i2c_clk()
554 	u32 target;  in init_clk_esdhc()  local
562 	target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |  in init_clk_esdhc()
565 	clock_set_target_val(USDHC1_CLK_ROOT, target);  in init_clk_esdhc()
567 	target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |  in init_clk_esdhc()
570 	clock_set_target_val(USDHC2_CLK_ROOT, target);  in init_clk_esdhc()
572 	target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |  in init_clk_esdhc()
575 	clock_set_target_val(USDHC3_CLK_ROOT, target);  in init_clk_esdhc()
585 	u32 target;  in init_clk_uart()  local
597 	target = CLK_ROOT_ON | UART1_CLK_ROOT_FROM_OSC_24M_CLK |  in init_clk_uart()
600 	clock_set_target_val(UART1_CLK_ROOT, target);  in init_clk_uart()
602 	target = CLK_ROOT_ON | UART2_CLK_ROOT_FROM_OSC_24M_CLK |  in init_clk_uart()
605 	clock_set_target_val(UART2_CLK_ROOT, target);  in init_clk_uart()
607 	target = CLK_ROOT_ON | UART3_CLK_ROOT_FROM_OSC_24M_CLK |  in init_clk_uart()
610 	clock_set_target_val(UART3_CLK_ROOT, target);  in init_clk_uart()
612 	target = CLK_ROOT_ON | UART4_CLK_ROOT_FROM_OSC_24M_CLK |  in init_clk_uart()
615 	clock_set_target_val(UART4_CLK_ROOT, target);  in init_clk_uart()
617 	target = CLK_ROOT_ON | UART5_CLK_ROOT_FROM_OSC_24M_CLK |  in init_clk_uart()
620 	clock_set_target_val(UART5_CLK_ROOT, target);  in init_clk_uart()
622 	target = CLK_ROOT_ON | UART6_CLK_ROOT_FROM_OSC_24M_CLK |  in init_clk_uart()
625 	clock_set_target_val(UART6_CLK_ROOT, target);  in init_clk_uart()
627 	target = CLK_ROOT_ON | UART7_CLK_ROOT_FROM_OSC_24M_CLK |  in init_clk_uart()
630 	clock_set_target_val(UART7_CLK_ROOT, target);  in init_clk_uart()
644 	u32 target;  in init_clk_weim()  local
650 	target = CLK_ROOT_ON | EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |  in init_clk_weim()
653 	clock_set_target_val(EIM_CLK_ROOT, target);  in init_clk_weim()
661 	u32 target;  in init_clk_ecspi()  local
670 	target = CLK_ROOT_ON | ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |  in init_clk_ecspi()
673 	clock_set_target_val(ECSPI1_CLK_ROOT, target);  in init_clk_ecspi()
675 	target = CLK_ROOT_ON | ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |  in init_clk_ecspi()
678 	clock_set_target_val(ECSPI2_CLK_ROOT, target);  in init_clk_ecspi()
680 	target = CLK_ROOT_ON | ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |  in init_clk_ecspi()
683 	clock_set_target_val(ECSPI3_CLK_ROOT, target);  in init_clk_ecspi()
685 	target = CLK_ROOT_ON | ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |  in init_clk_ecspi()
688 	clock_set_target_val(ECSPI4_CLK_ROOT, target);  in init_clk_ecspi()
699 	u32 target;  in init_clk_wdog()  local
708 	target = CLK_ROOT_ON | WDOG_CLK_ROOT_FROM_OSC_24M_CLK |  in init_clk_wdog()
711 	clock_set_target_val(WDOG_CLK_ROOT, target);  in init_clk_wdog()
723 	u32 target;  in init_clk_epdc()  local
729 	target = CLK_ROOT_ON | EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |  in init_clk_epdc()
732 	clock_set_target_val(EPDC_PIXEL_CLK_ROOT, target);  in init_clk_epdc()
855 	u32 target;  in set_clk_qspi()  local
861 	target = CLK_ROOT_ON | QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |  in set_clk_qspi()
864 	clock_set_target_val(QSPI_CLK_ROOT, target);  in set_clk_qspi()
874 	u32 target;  in set_clk_nand()  local
881 	target = CLK_ROOT_ON | NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK |  in set_clk_nand()
884 	clock_set_target_val(NAND_CLK_ROOT, target);  in set_clk_nand()
900 	u32 target;  in mxs_set_lcdclk()  local
950 	target = CLK_ROOT_ON | LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK |  in mxs_set_lcdclk()
952 	clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, target);  in mxs_set_lcdclk()
960 	u32 target;  in set_clk_enet()  local
990 	target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |  in set_clk_enet()
993 	clock_set_target_val(ENET_AXI_CLK_ROOT, target);  in set_clk_enet()
995 	target = CLK_ROOT_ON | enet1_ref |  in set_clk_enet()
998 	clock_set_target_val(ENET1_REF_CLK_ROOT, target);  in set_clk_enet()
1000 	target = CLK_ROOT_ON | ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |  in set_clk_enet()
1003 	clock_set_target_val(ENET1_TIME_CLK_ROOT, target);  in set_clk_enet()
1005 	target = CLK_ROOT_ON | enet2_ref |  in set_clk_enet()
1008 	clock_set_target_val(ENET2_REF_CLK_ROOT, target);  in set_clk_enet()
1010 	target = CLK_ROOT_ON | ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |  in set_clk_enet()
1013 	clock_set_target_val(ENET2_TIME_CLK_ROOT, target);  in set_clk_enet()
1016 	target = CLK_ROOT_ON |  in set_clk_enet()
1020 	clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target);  in set_clk_enet()