68 	clock_enable(CCGR_OCOTP, enable);  in enable_ocotp_clk()
83 		clock_enable(CCGR_USB_HSIC, 0);  in enable_usboh3_clk()
93 		clock_enable(CCGR_USB_CTRL, 1);  in enable_usboh3_clk()
94 		clock_enable(CCGR_USB_HSIC, 1);  in enable_usboh3_clk()
95 		clock_enable(CCGR_USB_PHY1, 1);  in enable_usboh3_clk()
96 		clock_enable(CCGR_USB_PHY2, 1);  in enable_usboh3_clk()
98 		clock_enable(CCGR_USB_CTRL, 0);  in enable_usboh3_clk()
99 		clock_enable(CCGR_USB_HSIC, 0);  in enable_usboh3_clk()
100 		clock_enable(CCGR_USB_PHY1, 0);  in enable_usboh3_clk()
101 		clock_enable(CCGR_USB_PHY2, 0);  in enable_usboh3_clk()
533 		clock_enable(CCGR_I2C1 + i2c_num, 0);  in enable_i2c_clk()
543 		clock_enable(CCGR_I2C1 + i2c_num, 1);  in enable_i2c_clk()
545 		clock_enable(CCGR_I2C1 + i2c_num, 0);  in enable_i2c_clk()
557 	clock_enable(CCGR_USDHC1, 0);  in init_clk_esdhc()
558 	clock_enable(CCGR_USDHC2, 0);  in init_clk_esdhc()
559 	clock_enable(CCGR_USDHC3, 0);  in init_clk_esdhc()
578 	clock_enable(CCGR_USDHC1, 1);  in init_clk_esdhc()
579 	clock_enable(CCGR_USDHC2, 1);  in init_clk_esdhc()
580 	clock_enable(CCGR_USDHC3, 1);  in init_clk_esdhc()
588 	clock_enable(CCGR_UART1, 0);  in init_clk_uart()
589 	clock_enable(CCGR_UART2, 0);  in init_clk_uart()
590 	clock_enable(CCGR_UART3, 0);  in init_clk_uart()
591 	clock_enable(CCGR_UART4, 0);  in init_clk_uart()
592 	clock_enable(CCGR_UART5, 0);  in init_clk_uart()
593 	clock_enable(CCGR_UART6, 0);  in init_clk_uart()
594 	clock_enable(CCGR_UART7, 0);  in init_clk_uart()
633 	clock_enable(CCGR_UART1, 1);  in init_clk_uart()
634 	clock_enable(CCGR_UART2, 1);  in init_clk_uart()
635 	clock_enable(CCGR_UART3, 1);  in init_clk_uart()
636 	clock_enable(CCGR_UART4, 1);  in init_clk_uart()
637 	clock_enable(CCGR_UART5, 1);  in init_clk_uart()
638 	clock_enable(CCGR_UART6, 1);  in init_clk_uart()
639 	clock_enable(CCGR_UART7, 1);  in init_clk_uart()
647 	clock_enable(CCGR_WEIM, 0);  in init_clk_weim()
656 	clock_enable(CCGR_WEIM, 1);  in init_clk_weim()
664 	clock_enable(CCGR_ECSPI1, 0);  in init_clk_ecspi()
665 	clock_enable(CCGR_ECSPI2, 0);  in init_clk_ecspi()
666 	clock_enable(CCGR_ECSPI3, 0);  in init_clk_ecspi()
667 	clock_enable(CCGR_ECSPI4, 0);  in init_clk_ecspi()
691 	clock_enable(CCGR_ECSPI1, 1);  in init_clk_ecspi()
692 	clock_enable(CCGR_ECSPI2, 1);  in init_clk_ecspi()
693 	clock_enable(CCGR_ECSPI3, 1);  in init_clk_ecspi()
694 	clock_enable(CCGR_ECSPI4, 1);  in init_clk_ecspi()
702 	clock_enable(CCGR_WDOG1, 0);  in init_clk_wdog()
703 	clock_enable(CCGR_WDOG2, 0);  in init_clk_wdog()
704 	clock_enable(CCGR_WDOG3, 0);  in init_clk_wdog()
705 	clock_enable(CCGR_WDOG4, 0);  in init_clk_wdog()
714 	clock_enable(CCGR_WDOG1, 1);  in init_clk_wdog()
715 	clock_enable(CCGR_WDOG2, 1);  in init_clk_wdog()
716 	clock_enable(CCGR_WDOG3, 1);  in init_clk_wdog()
717 	clock_enable(CCGR_WDOG4, 1);  in init_clk_wdog()
726 	clock_enable(CCGR_EPDC, 0);  in init_clk_epdc()
735 	clock_enable(CCGR_EPDC, 1);  in init_clk_epdc()
858 	clock_enable(CCGR_QSPI, 0);  in set_clk_qspi()
867 	clock_enable(CCGR_QSPI, 1);  in set_clk_qspi()
877 	clock_enable(CCGR_RAWNAND, 0);  in set_clk_nand()
887 	clock_enable(CCGR_RAWNAND, 1);  in set_clk_nand()
904 	clock_enable(CCGR_LCDIF, 0);  in mxs_set_lcdclk()
954 	clock_enable(CCGR_LCDIF, 1);  in mxs_set_lcdclk()
965 	clock_enable(CCGR_ENET1, 0);  in set_clk_enet()
966 	clock_enable(CCGR_ENET2, 0);  in set_clk_enet()
1023 	clock_enable(CCGR_ENET1, 1);  in set_clk_enet()
1024 	clock_enable(CCGR_ENET2, 1);  in set_clk_enet()
1065 	clock_enable(CCGR_SNVS, 1);  in clock_init()
1068 	clock_enable(CCGR_RAWNAND, 1);  in clock_init()
1072 		clock_enable(CCGR_RDC, 1);  in clock_init()
1073 		clock_enable(CCGR_SEMA1, 1);  in clock_init()
1074 		clock_enable(CCGR_SEMA2, 1);  in clock_init()
1082 		clock_enable(CCGR_CAAM, 1);  in hab_caam_clock_enable()
1084 		clock_enable(CCGR_CAAM, 0);  in hab_caam_clock_enable()
1091 	clock_enable(CCGR_EPDC, 1);  in epdc_clock_enable()
1095 	clock_enable(CCGR_EPDC, 0);  in epdc_clock_disable()