19 struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)  variable
116 		reg = readl(&ccm_anatop->pll_arm);  in decode_pll()
130 		reg = readl(&ccm_anatop->pll_480);  in decode_pll()
145 		reg = readl(&ccm_anatop->pll_enet);  in decode_pll()
156 		reg = readl(&ccm_anatop->pll_ddr);  in decode_pll()
161 		num = ccm_anatop->pll_ddr_num;  in decode_pll()
162 		denom = ccm_anatop->pll_ddr_denom;  in decode_pll()
189 	reg = readl(&ccm_anatop->pll_480);  in mxc_get_pll_sys_derive()
209 		reg = readl(&ccm_anatop->pfd_480a);  in mxc_get_pll_sys_derive()
218 		reg = readl(&ccm_anatop->pfd_480a);  in mxc_get_pll_sys_derive()
224 		reg = readl(&ccm_anatop->pfd_480a);  in mxc_get_pll_sys_derive()
233 		reg = readl(&ccm_anatop->pfd_480a);  in mxc_get_pll_sys_derive()
239 		reg = readl(&ccm_anatop->pfd_480a);  in mxc_get_pll_sys_derive()
248 		reg = readl(&ccm_anatop->pfd_480a);  in mxc_get_pll_sys_derive()
254 		reg = readl(&ccm_anatop->pfd_480a);  in mxc_get_pll_sys_derive()
261 		reg = readl(&ccm_anatop->pfd_480b);  in mxc_get_pll_sys_derive()
268 		reg = readl(&ccm_anatop->pfd_480b);  in mxc_get_pll_sys_derive()
275 		reg = readl(&ccm_anatop->pfd_480b);  in mxc_get_pll_sys_derive()
282 		reg = readl(&ccm_anatop->pfd_480b);  in mxc_get_pll_sys_derive()
301 	reg = readl(&ccm_anatop->pll_enet);  in mxc_get_pll_enet_derive()
345 	reg = readl(&ccm_anatop->pll_ddr);  in mxc_get_pll_ddr_derive()
744 	reg = readl(&ccm_anatop->pll_enet);  in enable_pll_enet()
748 		writel(reg, &ccm_anatop->pll_enet);  in enable_pll_enet()
751 			if (readl(&ccm_anatop->pll_enet) & ANADIG_PLL_LOCK)  in enable_pll_enet()
763 	writel(CCM_ANALOG_PLL_ENET_BYPASS_MASK, &ccm_anatop->pll_enet_clr);  in enable_pll_enet()
772 	       &ccm_anatop->pll_enet_set);  in enable_pll_enet()
792 		&ccm_anatop->pll_video_clr);  in enable_pll_video()
800 			&ccm_anatop->pll_video_set);  in enable_pll_video()
806 			&ccm_anatop->pll_video_set);  in enable_pll_video()
812 			&ccm_anatop->pll_video_set);  in enable_pll_video()
818 			&ccm_anatop->pll_video_set);  in enable_pll_video()
825 			&ccm_anatop->pll_video_set);  in enable_pll_video()
830 		&ccm_anatop->pll_video_num);  in enable_pll_video()
833 		&ccm_anatop->pll_video_denom);  in enable_pll_video()
839 		reg = readl(&ccm_anatop->pll_video);  in enable_pll_video()
843 					&ccm_anatop->pll_video_set);  in enable_pll_video()
1046 	reg = readl(&ccm_anatop->pfd_480b);  in clock_init()
1052 	writel(reg, &ccm_anatop->pfd_480b);  in clock_init()