Lines Matching +full:imx6sx +full:- +full:ccm
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/imx-regs.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/mach-imx/dma.h>
18 #include <asm/mach-imx/hab.h>
63 return readl(&scu->config) & 3; in get_nr_cpus()
69 u32 reg = readl(&anatop->digprog_sololite); in get_cpu_rev()
74 reg = readl(&anatop->digprog); in get_cpu_rev()
76 cfg = readl(&scu->config) & 3; in get_cpu_rev()
92 major--; in get_cpu_rev()
103 * defines a 2-bit SPEED_GRADING
126 struct fuse_bank *bank = &ocotp->bank[0]; in get_cpu_speed_grade_hz()
128 (struct fuse_bank0_regs *)bank->fuse_regs; in get_cpu_speed_grade_hz()
131 val = readl(&fuse->cfg3); in get_cpu_speed_grade_hz()
160 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */ in get_cpu_speed_grade_hz()
167 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */ in get_cpu_speed_grade_hz()
176 * defines a 2-bit Temperature Grade
185 struct fuse_bank *bank = &ocotp->bank[1]; in get_cpu_temp_grade()
187 (struct fuse_bank1_regs *)bank->fuse_regs; in get_cpu_temp_grade()
190 val = readl(&fuse->mem0); in get_cpu_temp_grade()
196 *minc = -40; in get_cpu_temp_grade()
199 *minc = -40; in get_cpu_temp_grade()
202 *minc = -20; in get_cpu_temp_grade()
236 reg = readl(&anatop->ana_misc2); in clear_ldo_ramp()
238 writel(reg, &anatop->ana_misc2); in clear_ldo_ramp()
251 u32 val, step, old, reg = readl(&anatop->reg_core); in set_ldo_voltage()
263 val = (mv - 700) / 25; in set_ldo_voltage()
278 return -EINVAL; in set_ldo_voltage()
282 step = abs(val - old); in set_ldo_voltage()
287 writel(reg, &anatop->reg_core); in set_ldo_voltage()
290 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per in set_ldo_voltage()
303 div = get_periph_clk() / val - 1; in set_ahb_rate()
304 reg = readl(&mxc_ccm->cbcdr); in set_ahb_rate()
307 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr); in set_ahb_rate()
314 reg = readl(&mxc_ccm->ccdr); in clear_mmdc_ch_mask()
321 writel(reg, &mxc_ccm->ccdr); in clear_mmdc_ch_mask()
330 struct fuse_bank *bank = &ocotp->bank[1]; in init_bandgap()
332 (struct fuse_bank1_regs *)bank->fuse_regs; in init_bandgap()
338 while (!(readl(&anatop->ana_misc0) & 0x80)) in init_bandgap()
345 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set); in init_bandgap()
349 * 000 - set REFTOP_VBGADJ[2:0] to 3b'110, in init_bandgap()
350 * 110 - set REFTOP_VBGADJ[2:0] to 3b'000, in init_bandgap()
351 * 001 - set REFTOP_VBGADJ[2:0] to 3b'001, in init_bandgap()
352 * 010 - set REFTOP_VBGADJ[2:0] to 3b'010, in init_bandgap()
353 * 011 - set REFTOP_VBGADJ[2:0] to 3b'011, in init_bandgap()
354 * 100 - set REFTOP_VBGADJ[2:0] to 3b'100, in init_bandgap()
355 * 101 - set REFTOP_VBGADJ[2:0] to 3b'101, in init_bandgap()
356 * 111 - set REFTOP_VBGADJ[2:0] to 3b'111, in init_bandgap()
359 val = readl(&fuse->mem0); in init_bandgap()
364 &anatop->ana_misc0_set); in init_bandgap()
370 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in arch_cpu_init() local
378 * Disable self-bias circuit in the analog bandap. in arch_cpu_init()
379 * The self-bias circuit is used by the bandgap during startup. in arch_cpu_init()
436 setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK); in arch_cpu_init()
441 setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL); in arch_cpu_init()
457 u32 soc_sbmr = readl(&src_regs->sbmr1); in mmc_get_boot_dev()
471 return -1; in mmc_get_boot_dev()
524 struct fuse_bank *bank = &ocotp->bank[4]; in imx_get_mac_from_fuse()
526 (struct fuse_bank4_regs *)bank->fuse_regs; in imx_get_mac_from_fuse()
529 u32 value = readl(&fuse->mac_addr2); in imx_get_mac_from_fuse()
535 value = readl(&fuse->mac_addr1); in imx_get_mac_from_fuse()
540 u32 value = readl(&fuse->mac_addr1); in imx_get_mac_from_fuse()
544 value = readl(&fuse->mac_addr0); in imx_get_mac_from_fuse()
593 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in s_init() local
614 reg = readl(&ccm->cbcmr); in s_init()
628 writel(mask480, &anatop->pfd_480_set); in s_init()
629 writel(mask528, &anatop->pfd_528_set); in s_init()
630 writel(mask480, &anatop->pfd_480_clr); in s_init()
631 writel(mask528, &anatop->pfd_528_clr); in s_init()
639 reg = readb(&hdmi->phy_conf0); in imx_enable_hdmi_phy()
641 writeb(reg, &hdmi->phy_conf0); in imx_enable_hdmi_phy()
644 writeb(reg, &hdmi->phy_conf0); in imx_enable_hdmi_phy()
647 writeb(reg, &hdmi->phy_conf0); in imx_enable_hdmi_phy()
648 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); in imx_enable_hdmi_phy()
659 reg = readl(&mxc_ccm->CCGR2); in imx_setup_hdmi()
662 writel(reg, &mxc_ccm->CCGR2); in imx_setup_hdmi()
663 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); in imx_setup_hdmi()
664 reg = readl(&mxc_ccm->chsccdr); in imx_setup_hdmi()
672 writel(reg, &mxc_ccm->chsccdr); in imx_setup_hdmi()
675 if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) { in imx_setup_hdmi()
677 writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz); in imx_setup_hdmi()
678 val = readb(&hdmi->fc_invidconf); in imx_setup_hdmi()
681 writeb(val, &hdmi->fc_invidconf); in imx_setup_hdmi()
691 writel(0xF00000CF, &iomux->gpr[4]); in gpr_init()
693 /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ in gpr_init()
694 writel(0x77177717, &iomux->gpr[6]); in gpr_init()
695 writel(0x77177717, &iomux->gpr[7]); in gpr_init()
697 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ in gpr_init()
698 writel(0x007F007F, &iomux->gpr[6]); in gpr_init()
699 writel(0x007F007F, &iomux->gpr[7]); in gpr_init()
710 return -EINVAL; in arch_auxiliary_core_up()
721 clrsetbits_le32(&src_reg->scr, SRC_SCR_M4C_NON_SCLR_RST_MASK, in arch_auxiliary_core_up()
732 val = readl(&src_reg->scr); in arch_auxiliary_core_check_up()