54 	struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;  in force_delay_measurement()  local
58 		writel(0x800, &mmdc1->mpmur0);  in force_delay_measurement()
91 	struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;  in mmdc_do_write_level_calibration()  local
105 		ldectrl[2] = readl(&mmdc1->mpwldectrl0);  in mmdc_do_write_level_calibration()
106 		ldectrl[3] = readl(&mmdc1->mpwldectrl1);  in mmdc_do_write_level_calibration()
130 		setbits_le32(&mmdc1->mdmisc, rwalat_max);  in mmdc_do_write_level_calibration()
158 		if (readl(&mmdc1->mpwlgcr) & 0x00000F00)  in mmdc_do_write_level_calibration()
167 	     ((readl(&mmdc1->mpwldectrl0) == 0x001F001F) &&  in mmdc_do_write_level_calibration()
168 	      (readl(&mmdc1->mpwldectrl1) == 0x001F001F)))) {  in mmdc_do_write_level_calibration()
173 			writel(ldectrl[2], &mmdc1->mpwldectrl0);  in mmdc_do_write_level_calibration()
174 			writel(ldectrl[3], &mmdc1->mpwldectrl1);  in mmdc_do_write_level_calibration()
200 		      readl(&mmdc1->mpwldectrl0));  in mmdc_do_write_level_calibration()
202 		      readl(&mmdc1->mpwldectrl1));  in mmdc_do_write_level_calibration()
209 		readl(&mmdc1->mpwldectrl0);  in mmdc_do_write_level_calibration()
210 		readl(&mmdc1->mpwldectrl1);  in mmdc_do_write_level_calibration()
228 	struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;  in mmdc_do_dqs_calibration()  local
323 		writel(initdelay, &mmdc1->mprddlctl);  in mmdc_do_dqs_calibration()
356 		setbits_le32(&mmdc1->mpdgctrl0, 1 << 30);  in mmdc_do_dqs_calibration()
372 	if ((sysinfo->dsize == 0x2) && (readl(&mmdc1->mpdgctrl0) & 0x00001000))  in mmdc_do_dqs_calibration()
378 		clrbits_le32(&mmdc1->mpdgctrl0, 1 << 30);  in mmdc_do_dqs_calibration()
390 		modify_dg_result(&mmdc1->mpdghwst0, &mmdc1->mpdghwst1,  in mmdc_do_dqs_calibration()
391 				 &mmdc1->mpdgctrl0);  in mmdc_do_dqs_calibration()
392 		modify_dg_result(&mmdc1->mpdghwst2, &mmdc1->mpdghwst3,  in mmdc_do_dqs_calibration()
393 				 &mmdc1->mpdgctrl1);  in mmdc_do_dqs_calibration()
433 	    (readl(&mmdc1->mprddlhwctl) & 0x0000000f))  in mmdc_do_dqs_calibration()
460 		writel(initdelay, &mmdc1->mpwrdlctl);  in mmdc_do_dqs_calibration()
487 	    (readl(&mmdc1->mpwrdlhwctl) & 0x0000000f))  in mmdc_do_dqs_calibration()
540 		debug("\tMPDGCTRL0 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl0));  in mmdc_do_dqs_calibration()
541 		debug("\tMPDGCTRL1 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl1));  in mmdc_do_dqs_calibration()
546 		debug("\tMPRDDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mprddlctl));  in mmdc_do_dqs_calibration()
550 		debug("\tMPWRDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mpwrdlctl));  in mmdc_do_dqs_calibration()
563 		debug("\tMPDGHWST0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst0));  in mmdc_do_dqs_calibration()
564 		debug("\tMPDGHWST1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst1));  in mmdc_do_dqs_calibration()
565 		debug("\tMPDGHWST2 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst2));  in mmdc_do_dqs_calibration()
566 		debug("\tMPDGHWST3 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst3));  in mmdc_do_dqs_calibration()
912 		mmdc1->entry = value;					  \
1203 	volatile struct mmdc_p_regs *mmdc1;  in mx6_ddr3_cfg()  local
1219 		mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;  in mx6_ddr3_cfg()
1507 	struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;  in mmdc_read_calibration()  local
1517 		calib->p1_mpwldectrl0 = readl(&mmdc1->mpwldectrl0);  in mmdc_read_calibration()
1518 		calib->p1_mpwldectrl1 = readl(&mmdc1->mpwldectrl1);  in mmdc_read_calibration()
1519 		calib->p1_mpdgctrl0 = readl(&mmdc1->mpdgctrl0);  in mmdc_read_calibration()
1520 		calib->p1_mpdgctrl1 = readl(&mmdc1->mpdgctrl1);  in mmdc_read_calibration()
1521 		calib->p1_mprddlctl = readl(&mmdc1->mprddlctl);  in mmdc_read_calibration()
1522 		calib->p1_mpwrdlctl = readl(&mmdc1->mpwrdlctl);  in mmdc_read_calibration()