20 	struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;  in reset_read_data_fifos()  local
23 	setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);  in reset_read_data_fifos()
24 	wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);  in reset_read_data_fifos()
26 	setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);  in reset_read_data_fifos()
27 	wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);  in reset_read_data_fifos()
32 	struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;  in precharge_all()  local
41 		writel(0x04008050, &mmdc0->mdscr);  in precharge_all()
42 		wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);  in precharge_all()
46 		writel(0x04008058, &mmdc0->mdscr);  in precharge_all()
47 		wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);  in precharge_all()
53 	struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;  in force_delay_measurement()  local
56 	writel(0x800, &mmdc0->mpmur0);  in force_delay_measurement()
90 	struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;  in mmdc_do_write_level_calibration()  local
102 	ldectrl[0] = readl(&mmdc0->mpwldectrl0);  in mmdc_do_write_level_calibration()
103 	ldectrl[1] = readl(&mmdc0->mpwldectrl1);  in mmdc_do_write_level_calibration()
110 	clrbits_le32(&mmdc0->mdpdc, 0xff00);  in mmdc_do_write_level_calibration()
113 	setbits_le32(&mmdc0->mapsr, 0x1);  in mmdc_do_write_level_calibration()
121 	esdmisc_val = readl(&mmdc0->mdref);  in mmdc_do_write_level_calibration()
122 	writel(0x0000C000, &mmdc0->mdref);  in mmdc_do_write_level_calibration()
123 	zq_val = readl(&mmdc0->mpzqhwctrl);  in mmdc_do_write_level_calibration()
124 	writel(zq_val & ~0x3, &mmdc0->mpzqhwctrl);  in mmdc_do_write_level_calibration()
128 	setbits_le32(&mmdc0->mdmisc, rwalat_max);  in mmdc_do_write_level_calibration()
140 	writel(0x00808231, &mmdc0->mdscr);  in mmdc_do_write_level_calibration()
143 	writel(0x00000001, &mmdc0->mpwlgcr);  in mmdc_do_write_level_calibration()
149 	wait_for_bit_le32(&mmdc0->mpwlgcr, 1 << 0, 0, 100, 0);  in mmdc_do_write_level_calibration()
155 	if (readl(&mmdc0->mpwlgcr) & 0x00000F00)  in mmdc_do_write_level_calibration()
164 	if ((readl(&mmdc0->mpwldectrl0) == 0x001F001F) &&  in mmdc_do_write_level_calibration()
165 	    (readl(&mmdc0->mpwldectrl1) == 0x001F001F) &&  in mmdc_do_write_level_calibration()
170 		writel(ldectrl[0], &mmdc0->mpwldectrl0);  in mmdc_do_write_level_calibration()
171 		writel(ldectrl[1], &mmdc0->mpwldectrl1);  in mmdc_do_write_level_calibration()
188 	writel((ddr_mr1 << 16) + 0x8031, &mmdc0->mdscr);  in mmdc_do_write_level_calibration()
191 	writel(esdmisc_val, &mmdc0->mdref);  in mmdc_do_write_level_calibration()
192 	writel(zq_val, &mmdc0->mpzqhwctrl);  in mmdc_do_write_level_calibration()
195 	      readl(&mmdc0->mpwldectrl0));  in mmdc_do_write_level_calibration()
197 	      readl(&mmdc0->mpwldectrl1));  in mmdc_do_write_level_calibration()
206 	readl(&mmdc0->mpwldectrl0);  in mmdc_do_write_level_calibration()
207 	readl(&mmdc0->mpwldectrl1);  in mmdc_do_write_level_calibration()
214 	setbits_le32(&mmdc0->mdpdc, 0x00005500);  in mmdc_do_write_level_calibration()
217 	clrbits_le32(&mmdc0->mapsr, 0x1);  in mmdc_do_write_level_calibration()
220 	writel(0, &mmdc0->mdscr);  in mmdc_do_write_level_calibration()
227 	struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;  in mmdc_do_dqs_calibration()  local
242 	cs0_enable_initial = readl(&mmdc0->mdctl) & 0x80000000;  in mmdc_do_dqs_calibration()
243 	cs1_enable_initial = readl(&mmdc0->mdctl) & 0x40000000;  in mmdc_do_dqs_calibration()
246 	clrbits_le32(&mmdc0->mdpdc, 0xff00);  in mmdc_do_dqs_calibration()
249 	setbits_le32(&mmdc0->mapsr, 0x1);  in mmdc_do_dqs_calibration()
262 	esdmisc_val = readl(&mmdc0->mdmisc);  in mmdc_do_dqs_calibration()
264 	setbits_le32(&mmdc0->mdmisc,  in mmdc_do_dqs_calibration()
268 	temp_ref = readl(&mmdc0->mdref);  in mmdc_do_dqs_calibration()
269 	writel(0x0000c000, &mmdc0->mdref);  in mmdc_do_dqs_calibration()
276 		writel(0x00008020, &mmdc0->mdscr);  in mmdc_do_dqs_calibration()
278 		writel(0x00008028, &mmdc0->mdscr);  in mmdc_do_dqs_calibration()
281 	wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);  in mmdc_do_dqs_calibration()
292 	if ((readl(&mmdc0->mdmisc) & 0x00100000) == 0)  in mmdc_do_dqs_calibration()
293 		clrbits_le32(&mmdc0->mdctl, 1 << 30);	/* clear SDE_1 */  in mmdc_do_dqs_calibration()
295 		clrbits_le32(&mmdc0->mdctl, 1 << 31);	/* clear SDE_0 */  in mmdc_do_dqs_calibration()
301 	cs0_enable = readl(&mmdc0->mdctl) & 0x80000000;  in mmdc_do_dqs_calibration()
302 	cs1_enable = readl(&mmdc0->mdctl) & 0x40000000;  in mmdc_do_dqs_calibration()
307 	writel(pddword, &mmdc0->mppdcmpr1);  in mmdc_do_dqs_calibration()
314 	setbits_le32(&mmdc0->mpswdar0, 1);  in mmdc_do_dqs_calibration()
315 	wait_for_bit_le32(&mmdc0->mpswdar0, 1 << 0, 0, 100, 0);  in mmdc_do_dqs_calibration()
321 	writel(initdelay, &mmdc0->mprddlctl);  in mmdc_do_dqs_calibration()
354 	setbits_le32(&mmdc0->mpdgctrl0, 1 << 30);  in mmdc_do_dqs_calibration()
359 	setbits_le32(&mmdc0->mpdgctrl0, 5 << 28);  in mmdc_do_dqs_calibration()
362 	wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0);  in mmdc_do_dqs_calibration()
369 	if (readl(&mmdc0->mpdgctrl0) & 0x00001000)  in mmdc_do_dqs_calibration()
376 	clrbits_le32(&mmdc0->mpdgctrl0, 1 << 30);  in mmdc_do_dqs_calibration()
385 	modify_dg_result(&mmdc0->mpdghwst0, &mmdc0->mpdghwst1,  in mmdc_do_dqs_calibration()
386 			 &mmdc0->mpdgctrl0);  in mmdc_do_dqs_calibration()
387 	modify_dg_result(&mmdc0->mpdghwst2, &mmdc0->mpdghwst3,  in mmdc_do_dqs_calibration()
388 			 &mmdc0->mpdgctrl1);  in mmdc_do_dqs_calibration()
418 	writel(0x00000030, &mmdc0->mprddlhwctl);  in mmdc_do_dqs_calibration()
426 	wait_for_bit_le32(&mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0);  in mmdc_do_dqs_calibration()
429 	if (readl(&mmdc0->mprddlhwctl) & 0x0000000f)  in mmdc_do_dqs_calibration()
458 	writel(initdelay, &mmdc0->mpwrdlctl);  in mmdc_do_dqs_calibration()
472 	writel(0x00000030, &mmdc0->mpwrdlhwctl);  in mmdc_do_dqs_calibration()
480 	wait_for_bit_le32(&mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0);  in mmdc_do_dqs_calibration()
483 	if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f)  in mmdc_do_dqs_calibration()
495 	setbits_le32(&mmdc0->mdpdc, 0x00005500);  in mmdc_do_dqs_calibration()
498 	clrbits_le32(&mmdc0->mapsr, 0x1);  in mmdc_do_dqs_calibration()
501 	writel(esdmisc_val, &mmdc0->mdmisc);  in mmdc_do_dqs_calibration()
516 		setbits_le32(&mmdc0->mdctl, 1 << 30);  in mmdc_do_dqs_calibration()
520 		setbits_le32(&mmdc0->mdctl, 1 << 31);  in mmdc_do_dqs_calibration()
523 	writel(temp_ref, &mmdc0->mdref);  in mmdc_do_dqs_calibration()
526 	writel(0x0, &mmdc0->mdscr);	/* CS0 */  in mmdc_do_dqs_calibration()
529 	wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 0, 100, 0);  in mmdc_do_dqs_calibration()
537 	debug("\tMPDGCTRL0 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl0));  in mmdc_do_dqs_calibration()
538 	debug("\tMPDGCTRL1 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl1));  in mmdc_do_dqs_calibration()
544 	debug("\tMPRDDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mprddlctl));  in mmdc_do_dqs_calibration()
548 	debug("\tMPWRDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mpwrdlctl));  in mmdc_do_dqs_calibration()
558 	debug("\tMPDGHWST0 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst0));  in mmdc_do_dqs_calibration()
559 	debug("\tMPDGHWST1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst1));  in mmdc_do_dqs_calibration()
560 	debug("\tMPDGHWST2 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst2));  in mmdc_do_dqs_calibration()
561 	debug("\tMPDGHWST3 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst3));  in mmdc_do_dqs_calibration()
973 	volatile struct mmdc_p_regs *mmdc0;  in mx6_lpddr2_cfg()  local
989 	mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;  in mx6_lpddr2_cfg()
1079 	mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;  in mx6_lpddr2_cfg()
1080 	mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;  in mx6_lpddr2_cfg()
1081 	mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;  in mx6_lpddr2_cfg()
1082 	mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;  in mx6_lpddr2_cfg()
1083 	mmdc0->mprddlctl = calib->p0_mprddlctl;  in mx6_lpddr2_cfg()
1084 	mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;  in mx6_lpddr2_cfg()
1085 	mmdc0->mpzqlp2ctl = calib->mpzqlp2ctl;  in mx6_lpddr2_cfg()
1088 	mmdc0->mprddqby0dl = 0x33333333;  in mx6_lpddr2_cfg()
1089 	mmdc0->mprddqby1dl = 0x33333333;  in mx6_lpddr2_cfg()
1091 		mmdc0->mprddqby2dl = 0x33333333;  in mx6_lpddr2_cfg()
1092 		mmdc0->mprddqby3dl = 0x33333333;  in mx6_lpddr2_cfg()
1096 	mmdc0->mpwrdqby0dl = 0xf3333333;  in mx6_lpddr2_cfg()
1097 	mmdc0->mpwrdqby1dl = 0xf3333333;  in mx6_lpddr2_cfg()
1099 		mmdc0->mpwrdqby2dl = 0xf3333333;  in mx6_lpddr2_cfg()
1100 		mmdc0->mpwrdqby3dl = 0xf3333333;  in mx6_lpddr2_cfg()
1107 	mmdc0->mpodtctrl = 0;  in mx6_lpddr2_cfg()
1111 	mmdc0->mpmur0 = val;  in mx6_lpddr2_cfg()
1114 	mmdc0->mdscr = (u32)(1 << 15); /* config request */  in mx6_lpddr2_cfg()
1117 	mmdc0->mdcfg0 = (trfc << 24) | (txsr << 16) | (txp << 13) |  in mx6_lpddr2_cfg()
1119 	mmdc0->mdcfg1 = (tras << 16) | (twr << 9) | (tmrd << 5) | twl;  in mx6_lpddr2_cfg()
1120 	mmdc0->mdcfg2 = (trtp << 6) | (twtr << 3) | trrd;  in mx6_lpddr2_cfg()
1121 	mmdc0->mdcfg3lp = (trc_lp << 16) | (trcd_lp << 8) |  in mx6_lpddr2_cfg()
1123 	mmdc0->mdotc = 0;  in mx6_lpddr2_cfg()
1125 	mmdc0->mdasp = cs0_end; /* CS addressing */  in mx6_lpddr2_cfg()
1128 	mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |  in mx6_lpddr2_cfg()
1133 	mmdc0->mdor = (sysinfo->sde_to_rst << 8) |  in mx6_lpddr2_cfg()
1142 	mmdc0->mdctl =  (lpddr2_cfg->rowaddr - 11) << 24 |	/* ROW */  in mx6_lpddr2_cfg()
1149 	mmdc0->mpzqhwctrl = val;  in mx6_lpddr2_cfg()
1152 	mmdc0->mdctl |= (1 << 31) |			     /* SDE_0 for CS0 */  in mx6_lpddr2_cfg()
1158 		mmdc0->mdscr = MR(63, 0, 3, cs);  in mx6_lpddr2_cfg()
1163 		mmdc0->mdscr = MR(val, 0, 3, cs);  in mx6_lpddr2_cfg()
1166 		mmdc0->mdscr = MR(val, 0, 3, cs);  in mx6_lpddr2_cfg()
1169 		mmdc0->mdscr = MR(val, 0, 3, cs);  in mx6_lpddr2_cfg()
1172 		mmdc0->mdscr = MR(val, 0, 3, cs);  in mx6_lpddr2_cfg()
1176 	mmdc0->mdpdc = (tcke & 0x7) << 16 |  in mx6_lpddr2_cfg()
1182 	mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */  in mx6_lpddr2_cfg()
1186 	mmdc0->mpzqhwctrl = val;  in mx6_lpddr2_cfg()
1189 	mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);  in mx6_lpddr2_cfg()
1192 	mmdc0->mdscr = 0x00000000;  in mx6_lpddr2_cfg()
1202 	volatile struct mmdc_p_regs *mmdc0;  in mx6_ddr3_cfg()  local
1217 	mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;  in mx6_ddr3_cfg()
1363 	mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;  in mx6_ddr3_cfg()
1364 	mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;  in mx6_ddr3_cfg()
1365 	mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;  in mx6_ddr3_cfg()
1366 	mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;  in mx6_ddr3_cfg()
1367 	mmdc0->mprddlctl = calib->p0_mprddlctl;  in mx6_ddr3_cfg()
1368 	mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;  in mx6_ddr3_cfg()
1379 	mmdc0->mprddqby0dl = 0x33333333;  in mx6_ddr3_cfg()
1380 	mmdc0->mprddqby1dl = 0x33333333;  in mx6_ddr3_cfg()
1382 		mmdc0->mprddqby2dl = 0x33333333;  in mx6_ddr3_cfg()
1383 		mmdc0->mprddqby3dl = 0x33333333;  in mx6_ddr3_cfg()
1395 	mmdc0->mpodtctrl = val;  in mx6_ddr3_cfg()
1401 	mmdc0->mpmur0 = val;  in mx6_ddr3_cfg()
1406 	mmdc0->mdscr = (u32)(1 << 15); /* config request */  in mx6_ddr3_cfg()
1409 	mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) |  in mx6_ddr3_cfg()
1411 	mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) |  in mx6_ddr3_cfg()
1414 	mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;  in mx6_ddr3_cfg()
1415 	mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) |  in mx6_ddr3_cfg()
1417 	mmdc0->mdasp = cs0_end; /* CS addressing */  in mx6_ddr3_cfg()
1420 	mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |  in mx6_ddr3_cfg()
1425 	mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) |  in mx6_ddr3_cfg()
1434 	mmdc0->mdctl =  (ddr3_cfg->rowaddr - 11) << 24 |	/* ROW */  in mx6_ddr3_cfg()
1441 	mmdc0->mpzqhwctrl = val;  in mx6_ddr3_cfg()
1446 	mmdc0->mdctl |= (1 << 31) |			     /* SDE_0 for CS0 */  in mx6_ddr3_cfg()
1455 		mmdc0->mdscr = MR(val, 2, 3, cs);  in mx6_ddr3_cfg()
1458 		mmdc0->mdscr = MR(0, 3, 3, cs);  in mx6_ddr3_cfg()
1463 		mmdc0->mdscr = MR(val, 1, 3, cs);  in mx6_ddr3_cfg()
1470 		mmdc0->mdscr = MR(val, 0, 3, cs);  in mx6_ddr3_cfg()
1473 		mmdc0->mdscr = MR(val, 0, 4, cs);  in mx6_ddr3_cfg()
1477 	mmdc0->mdpdc = (tcke & 0x7) << 16 |  in mx6_ddr3_cfg()
1484 		mmdc0->mdpdc |= (1 << 7); /* SLOW_PD */  in mx6_ddr3_cfg()
1485 	mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */  in mx6_ddr3_cfg()
1489 	mmdc0->mpzqhwctrl = val;  in mx6_ddr3_cfg()
1494 	mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);  in mx6_ddr3_cfg()
1497 	mmdc0->mdscr = 0x00000000;  in mx6_ddr3_cfg()
1506 	struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;  in mmdc_read_calibration()  local
1509 	calib->p0_mpwldectrl0 = readl(&mmdc0->mpwldectrl0);  in mmdc_read_calibration()
1510 	calib->p0_mpwldectrl1 = readl(&mmdc0->mpwldectrl1);  in mmdc_read_calibration()
1511 	calib->p0_mpdgctrl0 = readl(&mmdc0->mpdgctrl0);  in mmdc_read_calibration()
1512 	calib->p0_mpdgctrl1 = readl(&mmdc0->mpdgctrl1);  in mmdc_read_calibration()
1513 	calib->p0_mprddlctl = readl(&mmdc0->mprddlctl);  in mmdc_read_calibration()
1514 	calib->p0_mpwrdlctl = readl(&mmdc0->mpwrdlctl);  in mmdc_read_calibration()