41 		writel(0x04008050, &mmdc0->mdscr);  in precharge_all()
42 		wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);  in precharge_all()
46 		writel(0x04008058, &mmdc0->mdscr);  in precharge_all()
47 		wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);  in precharge_all()
140 	writel(0x00808231, &mmdc0->mdscr);  in mmdc_do_write_level_calibration()
188 	writel((ddr_mr1 << 16) + 0x8031, &mmdc0->mdscr);  in mmdc_do_write_level_calibration()
220 	writel(0, &mmdc0->mdscr);  in mmdc_do_write_level_calibration()
276 		writel(0x00008020, &mmdc0->mdscr);  in mmdc_do_dqs_calibration()
278 		writel(0x00008028, &mmdc0->mdscr);  in mmdc_do_dqs_calibration()
281 	wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);  in mmdc_do_dqs_calibration()
526 	writel(0x0, &mmdc0->mdscr);	/* CS0 */  in mmdc_do_dqs_calibration()
529 	wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 0, 100, 0);  in mmdc_do_dqs_calibration()
1114 	mmdc0->mdscr = (u32)(1 << 15); /* config request */  in mx6_lpddr2_cfg()
1158 		mmdc0->mdscr = MR(63, 0, 3, cs);  in mx6_lpddr2_cfg()
1163 		mmdc0->mdscr = MR(val, 0, 3, cs);  in mx6_lpddr2_cfg()
1166 		mmdc0->mdscr = MR(val, 0, 3, cs);  in mx6_lpddr2_cfg()
1169 		mmdc0->mdscr = MR(val, 0, 3, cs);  in mx6_lpddr2_cfg()
1172 		mmdc0->mdscr = MR(val, 0, 3, cs);  in mx6_lpddr2_cfg()
1192 	mmdc0->mdscr = 0x00000000;  in mx6_lpddr2_cfg()
1406 	mmdc0->mdscr = (u32)(1 << 15); /* config request */  in mx6_ddr3_cfg()
1455 		mmdc0->mdscr = MR(val, 2, 3, cs);  in mx6_ddr3_cfg()
1458 		mmdc0->mdscr = MR(0, 3, 3, cs);  in mx6_ddr3_cfg()
1463 		mmdc0->mdscr = MR(val, 1, 3, cs);  in mx6_ddr3_cfg()
1470 		mmdc0->mdscr = MR(val, 0, 3, cs);  in mx6_ddr3_cfg()
1473 		mmdc0->mdscr = MR(val, 0, 4, cs);  in mx6_ddr3_cfg()
1497 	mmdc0->mdscr = 0x00000000;  in mx6_ddr3_cfg()