115 	debug("Starting write leveling calibration.\n");  in mmdc_do_write_level_calibration()
161 	debug("Ending write leveling calibration. Error mask: 0x%x\n", errors);  in mmdc_do_write_level_calibration()
169 …debug("Cal seems to have soft-failed due to memory not supporting write leveling on all channels. …  in mmdc_do_write_level_calibration()
194 	debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n",  in mmdc_do_write_level_calibration()
196 	debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",  in mmdc_do_write_level_calibration()
199 		debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n",  in mmdc_do_write_level_calibration()
201 		debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",  in mmdc_do_write_level_calibration()
333 	debug("Starting Read DQS Gating calibration.\n");  in mmdc_do_dqs_calibration()
395 	debug("Ending Read DQS Gating calibration. Error mask: 0x%x\n", errors);  in mmdc_do_dqs_calibration()
402 	debug("Starting Read Delay calibration.\n");  in mmdc_do_dqs_calibration()
436 	debug("Ending Read Delay calibration. Error mask: 0x%x\n", errors);  in mmdc_do_dqs_calibration()
443 	debug("Starting Write Delay calibration.\n");  in mmdc_do_dqs_calibration()
490 	debug("Ending Write Delay calibration. Error mask: 0x%x\n", errors);  in mmdc_do_dqs_calibration()
535 	debug("MMDC registers updated from calibration\n");  in mmdc_do_dqs_calibration()
536 	debug("Read DQS gating calibration:\n");  in mmdc_do_dqs_calibration()
537 	debug("\tMPDGCTRL0 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl0));  in mmdc_do_dqs_calibration()
538 	debug("\tMPDGCTRL1 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl1));  in mmdc_do_dqs_calibration()
540 		debug("\tMPDGCTRL0 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl0));  in mmdc_do_dqs_calibration()
541 		debug("\tMPDGCTRL1 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl1));  in mmdc_do_dqs_calibration()
543 	debug("Read calibration:\n");  in mmdc_do_dqs_calibration()
544 	debug("\tMPRDDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mprddlctl));  in mmdc_do_dqs_calibration()
546 		debug("\tMPRDDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mprddlctl));  in mmdc_do_dqs_calibration()
547 	debug("Write calibration:\n");  in mmdc_do_dqs_calibration()
548 	debug("\tMPWRDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mpwrdlctl));  in mmdc_do_dqs_calibration()
550 		debug("\tMPWRDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mpwrdlctl));  in mmdc_do_dqs_calibration()
557 	debug("Status registers bounds for read DQS gating:\n");  in mmdc_do_dqs_calibration()
558 	debug("\tMPDGHWST0 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst0));  in mmdc_do_dqs_calibration()
559 	debug("\tMPDGHWST1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst1));  in mmdc_do_dqs_calibration()
560 	debug("\tMPDGHWST2 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst2));  in mmdc_do_dqs_calibration()
561 	debug("\tMPDGHWST3 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst3));  in mmdc_do_dqs_calibration()
563 		debug("\tMPDGHWST0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst0));  in mmdc_do_dqs_calibration()
564 		debug("\tMPDGHWST1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst1));  in mmdc_do_dqs_calibration()
565 		debug("\tMPDGHWST2 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst2));  in mmdc_do_dqs_calibration()
566 		debug("\tMPDGHWST3 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst3));  in mmdc_do_dqs_calibration()
569 	debug("Final do_dqs_calibration error mask: 0x%x\n", errors);  in mmdc_do_dqs_calibration()
1049 	debug("density:%d Gb (%d Gb per chip)\n",  in mx6_lpddr2_cfg()
1051 	debug("clock: %dMHz (%d ps)\n", clock, clkper);  in mx6_lpddr2_cfg()
1052 	debug("memspd:%d\n", lpddr2_cfg->mem_speed);  in mx6_lpddr2_cfg()
1053 	debug("trcd_lp=%d\n", trcd_lp);  in mx6_lpddr2_cfg()
1054 	debug("trppb_lp=%d\n", trppb_lp);  in mx6_lpddr2_cfg()
1055 	debug("trpab_lp=%d\n", trpab_lp);  in mx6_lpddr2_cfg()
1056 	debug("trc_lp=%d\n", trc_lp);  in mx6_lpddr2_cfg()
1057 	debug("tcke=%d\n", tcke);  in mx6_lpddr2_cfg()
1058 	debug("tcksrx=%d\n", tcksrx);  in mx6_lpddr2_cfg()
1059 	debug("tcksre=%d\n", tcksre);  in mx6_lpddr2_cfg()
1060 	debug("trfc=%d\n", trfc);  in mx6_lpddr2_cfg()
1061 	debug("txsr=%d\n", txsr);  in mx6_lpddr2_cfg()
1062 	debug("txp=%d\n", txp);  in mx6_lpddr2_cfg()
1063 	debug("tfaw=%d\n", tfaw);  in mx6_lpddr2_cfg()
1064 	debug("tcl=%d\n", tcl);  in mx6_lpddr2_cfg()
1065 	debug("tras=%d\n", tras);  in mx6_lpddr2_cfg()
1066 	debug("twr=%d\n", twr);  in mx6_lpddr2_cfg()
1067 	debug("tmrd=%d\n", tmrd);  in mx6_lpddr2_cfg()
1068 	debug("twl=%d\n", twl);  in mx6_lpddr2_cfg()
1069 	debug("trtp=%d\n", trtp);  in mx6_lpddr2_cfg()
1070 	debug("twtr=%d\n", twtr);  in mx6_lpddr2_cfg()
1071 	debug("trrd=%d\n", trrd);  in mx6_lpddr2_cfg()
1072 	debug("cs0_end=%d\n", cs0_end);  in mx6_lpddr2_cfg()
1073 	debug("ncs=%d\n", sysinfo->ncs);  in mx6_lpddr2_cfg()
1320 	debug("density:%d Gb (%d Gb per chip)\n",  in mx6_ddr3_cfg()
1322 	debug("clock: %dMHz (%d ps)\n", clock, clkper);  in mx6_ddr3_cfg()
1323 	debug("memspd:%d\n", mem_speed);  in mx6_ddr3_cfg()
1324 	debug("tcke=%d\n", tcke);  in mx6_ddr3_cfg()
1325 	debug("tcksrx=%d\n", tcksrx);  in mx6_ddr3_cfg()
1326 	debug("tcksre=%d\n", tcksre);  in mx6_ddr3_cfg()
1327 	debug("taofpd=%d\n", taofpd);  in mx6_ddr3_cfg()
1328 	debug("taonpd=%d\n", taonpd);  in mx6_ddr3_cfg()
1329 	debug("todtlon=%d\n", todtlon);  in mx6_ddr3_cfg()
1330 	debug("tanpd=%d\n", tanpd);  in mx6_ddr3_cfg()
1331 	debug("taxpd=%d\n", taxpd);  in mx6_ddr3_cfg()
1332 	debug("trfc=%d\n", trfc);  in mx6_ddr3_cfg()
1333 	debug("txs=%d\n", txs);  in mx6_ddr3_cfg()
1334 	debug("txp=%d\n", txp);  in mx6_ddr3_cfg()
1335 	debug("txpdll=%d\n", txpdll);  in mx6_ddr3_cfg()
1336 	debug("tfaw=%d\n", tfaw);  in mx6_ddr3_cfg()
1337 	debug("tcl=%d\n", tcl);  in mx6_ddr3_cfg()
1338 	debug("trcd=%d\n", trcd);  in mx6_ddr3_cfg()
1339 	debug("trp=%d\n", trp);  in mx6_ddr3_cfg()
1340 	debug("trc=%d\n", trc);  in mx6_ddr3_cfg()
1341 	debug("tras=%d\n", tras);  in mx6_ddr3_cfg()
1342 	debug("twr=%d\n", twr);  in mx6_ddr3_cfg()
1343 	debug("tmrd=%d\n", tmrd);  in mx6_ddr3_cfg()
1344 	debug("tcwl=%d\n", tcwl);  in mx6_ddr3_cfg()
1345 	debug("tdllk=%d\n", tdllk);  in mx6_ddr3_cfg()
1346 	debug("trtp=%d\n", trtp);  in mx6_ddr3_cfg()
1347 	debug("twtr=%d\n", twtr);  in mx6_ddr3_cfg()
1348 	debug("trrd=%d\n", trrd);  in mx6_ddr3_cfg()
1349 	debug("txpr=%d\n", txpr);  in mx6_ddr3_cfg()
1350 	debug("cs0_end=%d\n", cs0_end);  in mx6_ddr3_cfg()
1351 	debug("ncs=%d\n", sysinfo->ncs);  in mx6_ddr3_cfg()
1352 	debug("Rtt_wr=%d\n", sysinfo->rtt_wr);  in mx6_ddr3_cfg()
1353 	debug("Rtt_nom=%d\n", sysinfo->rtt_nom);  in mx6_ddr3_cfg()
1354 	debug("SRT=%d\n", ddr3_cfg->SRT);  in mx6_ddr3_cfg()
1355 	debug("twr=%d\n", twr);  in mx6_ddr3_cfg()
1454 		debug("MR2 CS%d: 0x%08x\n", cs, (u32)MR(val, 2, 3, cs));  in mx6_ddr3_cfg()
1457 		debug("MR3 CS%d: 0x%08x\n", cs, (u32)MR(0, 3, 3, cs));  in mx6_ddr3_cfg()
1462 		debug("MR1 CS%d: 0x%08x\n", cs, (u32)MR(val, 1, 3, cs));  in mx6_ddr3_cfg()
1469 		debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs));  in mx6_ddr3_cfg()