Lines Matching +full:pico +full:- +full:seconds
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/mx6-ddr.h>
23 setbits_le32(&mmdc0->mpdgctrl0, 1 << 31); in reset_read_data_fifos()
24 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0); in reset_read_data_fifos()
26 setbits_le32(&mmdc0->mpdgctrl0, 1 << 31); in reset_read_data_fifos()
27 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0); in reset_read_data_fifos()
35 * Issue the Precharge-All command to the DDR device for both in precharge_all()
41 writel(0x04008050, &mmdc0->mdscr); in precharge_all()
42 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0); in precharge_all()
46 writel(0x04008058, &mmdc0->mdscr); in precharge_all()
47 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0); in precharge_all()
56 writel(0x800, &mmdc0->mpmur0); in force_delay_measurement()
58 writel(0x800, &mmdc1->mpmur0); in force_delay_measurement()
67 * (HW_DG_LOWx + HW_DG_UPx)/2 to reflecting (HW_DG_UPx - 0x80) in modify_dg_result()
73 dg_tmp_val = ((readl(reg_st0) & 0x07ff0000) >> 16) - 0xc0; in modify_dg_result()
79 dg_tmp_val = ((readl(reg_st1) & 0x07ff0000) >> 16) - 0xc0; in modify_dg_result()
102 ldectrl[0] = readl(&mmdc0->mpwldectrl0); in mmdc_do_write_level_calibration()
103 ldectrl[1] = readl(&mmdc0->mpwldectrl1); in mmdc_do_write_level_calibration()
104 if (sysinfo->dsize == 2) { in mmdc_do_write_level_calibration()
105 ldectrl[2] = readl(&mmdc1->mpwldectrl0); in mmdc_do_write_level_calibration()
106 ldectrl[3] = readl(&mmdc1->mpwldectrl1); in mmdc_do_write_level_calibration()
110 clrbits_le32(&mmdc0->mdpdc, 0xff00); in mmdc_do_write_level_calibration()
113 setbits_le32(&mmdc0->mapsr, 0x1); in mmdc_do_write_level_calibration()
121 esdmisc_val = readl(&mmdc0->mdref); in mmdc_do_write_level_calibration()
122 writel(0x0000C000, &mmdc0->mdref); in mmdc_do_write_level_calibration()
123 zq_val = readl(&mmdc0->mpzqhwctrl); in mmdc_do_write_level_calibration()
124 writel(zq_val & ~0x3, &mmdc0->mpzqhwctrl); in mmdc_do_write_level_calibration()
128 setbits_le32(&mmdc0->mdmisc, rwalat_max); in mmdc_do_write_level_calibration()
129 if (sysinfo->dsize == 2) in mmdc_do_write_level_calibration()
130 setbits_le32(&mmdc1->mdmisc, rwalat_max); in mmdc_do_write_level_calibration()
132 * 4 & 5. Configure the external DDR device to enter write-leveling in mmdc_do_write_level_calibration()
140 writel(0x00808231, &mmdc0->mdscr); in mmdc_do_write_level_calibration()
143 writel(0x00000001, &mmdc0->mpwlgcr); in mmdc_do_write_level_calibration()
146 * 7. Upon completion of this process the MMDC de-asserts in mmdc_do_write_level_calibration()
149 wait_for_bit_le32(&mmdc0->mpwlgcr, 1 << 0, 0, 100, 0); in mmdc_do_write_level_calibration()
155 if (readl(&mmdc0->mpwlgcr) & 0x00000F00) in mmdc_do_write_level_calibration()
157 if (sysinfo->dsize == 2) in mmdc_do_write_level_calibration()
158 if (readl(&mmdc1->mpwlgcr) & 0x00000F00) in mmdc_do_write_level_calibration()
164 if ((readl(&mmdc0->mpwldectrl0) == 0x001F001F) && in mmdc_do_write_level_calibration()
165 (readl(&mmdc0->mpwldectrl1) == 0x001F001F) && in mmdc_do_write_level_calibration()
166 ((sysinfo->dsize < 2) || in mmdc_do_write_level_calibration()
167 ((readl(&mmdc1->mpwldectrl0) == 0x001F001F) && in mmdc_do_write_level_calibration()
168 (readl(&mmdc1->mpwldectrl1) == 0x001F001F)))) { in mmdc_do_write_level_calibration()
169 …debug("Cal seems to have soft-failed due to memory not supporting write leveling on all channels. … in mmdc_do_write_level_calibration()
170 writel(ldectrl[0], &mmdc0->mpwldectrl0); in mmdc_do_write_level_calibration()
171 writel(ldectrl[1], &mmdc0->mpwldectrl1); in mmdc_do_write_level_calibration()
172 if (sysinfo->dsize == 2) { in mmdc_do_write_level_calibration()
173 writel(ldectrl[2], &mmdc1->mpwldectrl0); in mmdc_do_write_level_calibration()
174 writel(ldectrl[3], &mmdc1->mpwldectrl1); in mmdc_do_write_level_calibration()
188 writel((ddr_mr1 << 16) + 0x8031, &mmdc0->mdscr); in mmdc_do_write_level_calibration()
190 /* re-enable auto refresh and zq cal */ in mmdc_do_write_level_calibration()
191 writel(esdmisc_val, &mmdc0->mdref); in mmdc_do_write_level_calibration()
192 writel(zq_val, &mmdc0->mpzqhwctrl); in mmdc_do_write_level_calibration()
195 readl(&mmdc0->mpwldectrl0)); in mmdc_do_write_level_calibration()
197 readl(&mmdc0->mpwldectrl1)); in mmdc_do_write_level_calibration()
198 if (sysinfo->dsize == 2) { in mmdc_do_write_level_calibration()
200 readl(&mmdc1->mpwldectrl0)); in mmdc_do_write_level_calibration()
202 readl(&mmdc1->mpwldectrl1)); in mmdc_do_write_level_calibration()
206 readl(&mmdc0->mpwldectrl0); in mmdc_do_write_level_calibration()
207 readl(&mmdc0->mpwldectrl1); in mmdc_do_write_level_calibration()
208 if (sysinfo->dsize == 2) { in mmdc_do_write_level_calibration()
209 readl(&mmdc1->mpwldectrl0); in mmdc_do_write_level_calibration()
210 readl(&mmdc1->mpwldectrl1); in mmdc_do_write_level_calibration()
214 setbits_le32(&mmdc0->mdpdc, 0x00005500); in mmdc_do_write_level_calibration()
217 clrbits_le32(&mmdc0->mapsr, 0x1); in mmdc_do_write_level_calibration()
220 writel(0, &mmdc0->mdscr); in mmdc_do_write_level_calibration()
242 cs0_enable_initial = readl(&mmdc0->mdctl) & 0x80000000; in mmdc_do_dqs_calibration()
243 cs1_enable_initial = readl(&mmdc0->mdctl) & 0x40000000; in mmdc_do_dqs_calibration()
246 clrbits_le32(&mmdc0->mdpdc, 0xff00); in mmdc_do_dqs_calibration()
249 setbits_le32(&mmdc0->mapsr, 0x1); in mmdc_do_dqs_calibration()
252 setbits_le32(&mx6_ddr_iomux->dram_sdqs0, 0x7000); in mmdc_do_dqs_calibration()
253 setbits_le32(&mx6_ddr_iomux->dram_sdqs1, 0x7000); in mmdc_do_dqs_calibration()
254 setbits_le32(&mx6_ddr_iomux->dram_sdqs2, 0x7000); in mmdc_do_dqs_calibration()
255 setbits_le32(&mx6_ddr_iomux->dram_sdqs3, 0x7000); in mmdc_do_dqs_calibration()
256 setbits_le32(&mx6_ddr_iomux->dram_sdqs4, 0x7000); in mmdc_do_dqs_calibration()
257 setbits_le32(&mx6_ddr_iomux->dram_sdqs5, 0x7000); in mmdc_do_dqs_calibration()
258 setbits_le32(&mx6_ddr_iomux->dram_sdqs6, 0x7000); in mmdc_do_dqs_calibration()
259 setbits_le32(&mx6_ddr_iomux->dram_sdqs7, 0x7000); in mmdc_do_dqs_calibration()
262 esdmisc_val = readl(&mmdc0->mdmisc); in mmdc_do_dqs_calibration()
264 setbits_le32(&mmdc0->mdmisc, in mmdc_do_dqs_calibration()
268 temp_ref = readl(&mmdc0->mdref); in mmdc_do_dqs_calibration()
269 writel(0x0000c000, &mmdc0->mdref); in mmdc_do_dqs_calibration()
276 writel(0x00008020, &mmdc0->mdscr); in mmdc_do_dqs_calibration()
278 writel(0x00008028, &mmdc0->mdscr); in mmdc_do_dqs_calibration()
281 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0); in mmdc_do_dqs_calibration()
289 * to avoid any potential issues. This will get re-enabled at end in mmdc_do_dqs_calibration()
292 if ((readl(&mmdc0->mdmisc) & 0x00100000) == 0) in mmdc_do_dqs_calibration()
293 clrbits_le32(&mmdc0->mdctl, 1 << 30); /* clear SDE_1 */ in mmdc_do_dqs_calibration()
295 clrbits_le32(&mmdc0->mdctl, 1 << 31); /* clear SDE_0 */ in mmdc_do_dqs_calibration()
301 cs0_enable = readl(&mmdc0->mdctl) & 0x80000000; in mmdc_do_dqs_calibration()
302 cs1_enable = readl(&mmdc0->mdctl) & 0x40000000; in mmdc_do_dqs_calibration()
306 /* Write the pre-defined value into MPPDCMPR1 */ in mmdc_do_dqs_calibration()
307 writel(pddword, &mmdc0->mppdcmpr1); in mmdc_do_dqs_calibration()
314 setbits_le32(&mmdc0->mpswdar0, 1); in mmdc_do_dqs_calibration()
315 wait_for_bit_le32(&mmdc0->mpswdar0, 1 << 0, 0, 100, 0); in mmdc_do_dqs_calibration()
318 * (will be calibrated later in the read delay-line calibration). in mmdc_do_dqs_calibration()
321 writel(initdelay, &mmdc0->mprddlctl); in mmdc_do_dqs_calibration()
322 if (sysinfo->dsize == 0x2) in mmdc_do_dqs_calibration()
323 writel(initdelay, &mmdc1->mprddlctl); in mmdc_do_dqs_calibration()
326 force_delay_measurement(sysinfo->dsize); in mmdc_do_dqs_calibration()
354 setbits_le32(&mmdc0->mpdgctrl0, 1 << 30); in mmdc_do_dqs_calibration()
355 if (sysinfo->dsize == 2) in mmdc_do_dqs_calibration()
356 setbits_le32(&mmdc1->mpdgctrl0, 1 << 30); in mmdc_do_dqs_calibration()
359 setbits_le32(&mmdc0->mpdgctrl0, 5 << 28); in mmdc_do_dqs_calibration()
362 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0); in mmdc_do_dqs_calibration()
369 if (readl(&mmdc0->mpdgctrl0) & 0x00001000) in mmdc_do_dqs_calibration()
372 if ((sysinfo->dsize == 0x2) && (readl(&mmdc1->mpdgctrl0) & 0x00001000)) in mmdc_do_dqs_calibration()
376 clrbits_le32(&mmdc0->mpdgctrl0, 1 << 30); in mmdc_do_dqs_calibration()
377 if (sysinfo->dsize == 2) in mmdc_do_dqs_calibration()
378 clrbits_le32(&mmdc1->mpdgctrl0, 1 << 30); in mmdc_do_dqs_calibration()
383 * reflecting (HW_DG_UPx - 0x80) in mmdc_do_dqs_calibration()
385 modify_dg_result(&mmdc0->mpdghwst0, &mmdc0->mpdghwst1, in mmdc_do_dqs_calibration()
386 &mmdc0->mpdgctrl0); in mmdc_do_dqs_calibration()
387 modify_dg_result(&mmdc0->mpdghwst2, &mmdc0->mpdghwst3, in mmdc_do_dqs_calibration()
388 &mmdc0->mpdgctrl1); in mmdc_do_dqs_calibration()
389 if (sysinfo->dsize == 0x2) { in mmdc_do_dqs_calibration()
390 modify_dg_result(&mmdc1->mpdghwst0, &mmdc1->mpdghwst1, in mmdc_do_dqs_calibration()
391 &mmdc1->mpdgctrl0); in mmdc_do_dqs_calibration()
392 modify_dg_result(&mmdc1->mpdghwst2, &mmdc1->mpdghwst3, in mmdc_do_dqs_calibration()
393 &mmdc1->mpdgctrl1); in mmdc_do_dqs_calibration()
407 * 4. Issue the Precharge-All command to the DDR device for both in mmdc_do_dqs_calibration()
414 * 9. Read delay-line calibration in mmdc_do_dqs_calibration()
418 writel(0x00000030, &mmdc0->mprddlhwctl); in mmdc_do_dqs_calibration()
426 wait_for_bit_le32(&mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0); in mmdc_do_dqs_calibration()
429 if (readl(&mmdc0->mprddlhwctl) & 0x0000000f) in mmdc_do_dqs_calibration()
432 if ((sysinfo->dsize == 0x2) && in mmdc_do_dqs_calibration()
433 (readl(&mmdc1->mprddlhwctl) & 0x0000000f)) in mmdc_do_dqs_calibration()
448 * 4. Issue the Precharge-All command to the DDR device for both in mmdc_do_dqs_calibration()
458 writel(initdelay, &mmdc0->mpwrdlctl); in mmdc_do_dqs_calibration()
459 if (sysinfo->dsize == 0x2) in mmdc_do_dqs_calibration()
460 writel(initdelay, &mmdc1->mpwrdlctl); in mmdc_do_dqs_calibration()
466 force_delay_measurement(sysinfo->dsize); in mmdc_do_dqs_calibration()
472 writel(0x00000030, &mmdc0->mpwrdlhwctl); in mmdc_do_dqs_calibration()
480 wait_for_bit_le32(&mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0); in mmdc_do_dqs_calibration()
483 if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f) in mmdc_do_dqs_calibration()
486 if ((sysinfo->dsize == 0x2) && in mmdc_do_dqs_calibration()
487 (readl(&mmdc1->mpwrdlhwctl) & 0x0000000f)) in mmdc_do_dqs_calibration()
495 setbits_le32(&mmdc0->mdpdc, 0x00005500); in mmdc_do_dqs_calibration()
498 clrbits_le32(&mmdc0->mapsr, 0x1); in mmdc_do_dqs_calibration()
501 writel(esdmisc_val, &mmdc0->mdmisc); in mmdc_do_dqs_calibration()
504 clrbits_le32(&mx6_ddr_iomux->dram_sdqs0, 0x7000); in mmdc_do_dqs_calibration()
505 clrbits_le32(&mx6_ddr_iomux->dram_sdqs1, 0x7000); in mmdc_do_dqs_calibration()
506 clrbits_le32(&mx6_ddr_iomux->dram_sdqs2, 0x7000); in mmdc_do_dqs_calibration()
507 clrbits_le32(&mx6_ddr_iomux->dram_sdqs3, 0x7000); in mmdc_do_dqs_calibration()
508 clrbits_le32(&mx6_ddr_iomux->dram_sdqs4, 0x7000); in mmdc_do_dqs_calibration()
509 clrbits_le32(&mx6_ddr_iomux->dram_sdqs5, 0x7000); in mmdc_do_dqs_calibration()
510 clrbits_le32(&mx6_ddr_iomux->dram_sdqs6, 0x7000); in mmdc_do_dqs_calibration()
511 clrbits_le32(&mx6_ddr_iomux->dram_sdqs7, 0x7000); in mmdc_do_dqs_calibration()
513 /* Re-enable SDE (chip selects) if they were set initially */ in mmdc_do_dqs_calibration()
516 setbits_le32(&mmdc0->mdctl, 1 << 30); in mmdc_do_dqs_calibration()
520 setbits_le32(&mmdc0->mdctl, 1 << 31); in mmdc_do_dqs_calibration()
522 /* Re-enable to auto refresh */ in mmdc_do_dqs_calibration()
523 writel(temp_ref, &mmdc0->mdref); in mmdc_do_dqs_calibration()
526 writel(0x0, &mmdc0->mdscr); /* CS0 */ in mmdc_do_dqs_calibration()
529 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 0, 100, 0); in mmdc_do_dqs_calibration()
537 debug("\tMPDGCTRL0 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl0)); in mmdc_do_dqs_calibration()
538 debug("\tMPDGCTRL1 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl1)); in mmdc_do_dqs_calibration()
539 if (sysinfo->dsize == 2) { in mmdc_do_dqs_calibration()
540 debug("\tMPDGCTRL0 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl0)); in mmdc_do_dqs_calibration()
541 debug("\tMPDGCTRL1 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl1)); in mmdc_do_dqs_calibration()
544 debug("\tMPRDDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mprddlctl)); in mmdc_do_dqs_calibration()
545 if (sysinfo->dsize == 2) in mmdc_do_dqs_calibration()
546 debug("\tMPRDDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mprddlctl)); in mmdc_do_dqs_calibration()
548 debug("\tMPWRDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mpwrdlctl)); in mmdc_do_dqs_calibration()
549 if (sysinfo->dsize == 2) in mmdc_do_dqs_calibration()
550 debug("\tMPWRDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mpwrdlctl)); in mmdc_do_dqs_calibration()
558 debug("\tMPDGHWST0 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst0)); in mmdc_do_dqs_calibration()
559 debug("\tMPDGHWST1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst1)); in mmdc_do_dqs_calibration()
560 debug("\tMPDGHWST2 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst2)); in mmdc_do_dqs_calibration()
561 debug("\tMPDGHWST3 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst3)); in mmdc_do_dqs_calibration()
562 if (sysinfo->dsize == 2) { in mmdc_do_dqs_calibration()
563 debug("\tMPDGHWST0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst0)); in mmdc_do_dqs_calibration()
564 debug("\tMPDGHWST1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst1)); in mmdc_do_dqs_calibration()
565 debug("\tMPDGHWST2 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst2)); in mmdc_do_dqs_calibration()
566 debug("\tMPDGHWST3 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst3)); in mmdc_do_dqs_calibration()
588 writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type); in mx6sx_dram_iocfg()
589 writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke); in mx6sx_dram_iocfg()
592 writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0); in mx6sx_dram_iocfg()
595 writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas); in mx6sx_dram_iocfg()
596 writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras); in mx6sx_dram_iocfg()
597 writel(grp->grp_addds, &mx6_grp_iomux->grp_addds); in mx6sx_dram_iocfg()
600 writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset); in mx6sx_dram_iocfg()
601 writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2); in mx6sx_dram_iocfg()
602 writel(ddr->dram_sdcke0, &mx6_ddr_iomux->dram_sdcke0); in mx6sx_dram_iocfg()
603 writel(ddr->dram_sdcke1, &mx6_ddr_iomux->dram_sdcke1); in mx6sx_dram_iocfg()
604 writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0); in mx6sx_dram_iocfg()
605 writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1); in mx6sx_dram_iocfg()
606 writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds); in mx6sx_dram_iocfg()
609 writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl); in mx6sx_dram_iocfg()
610 writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0); in mx6sx_dram_iocfg()
611 writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1); in mx6sx_dram_iocfg()
613 writel(ddr->dram_sdqs2, &mx6_ddr_iomux->dram_sdqs2); in mx6sx_dram_iocfg()
614 writel(ddr->dram_sdqs3, &mx6_ddr_iomux->dram_sdqs3); in mx6sx_dram_iocfg()
618 writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode); in mx6sx_dram_iocfg()
619 writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds); in mx6sx_dram_iocfg()
620 writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds); in mx6sx_dram_iocfg()
622 writel(grp->grp_b2ds, &mx6_grp_iomux->grp_b2ds); in mx6sx_dram_iocfg()
623 writel(grp->grp_b3ds, &mx6_grp_iomux->grp_b3ds); in mx6sx_dram_iocfg()
625 writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0); in mx6sx_dram_iocfg()
626 writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1); in mx6sx_dram_iocfg()
628 writel(ddr->dram_dqm2, &mx6_ddr_iomux->dram_dqm2); in mx6sx_dram_iocfg()
629 writel(ddr->dram_dqm3, &mx6_ddr_iomux->dram_dqm3); in mx6sx_dram_iocfg()
646 writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type); in mx6ul_dram_iocfg()
647 writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke); in mx6ul_dram_iocfg()
650 writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0); in mx6ul_dram_iocfg()
653 writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas); in mx6ul_dram_iocfg()
654 writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras); in mx6ul_dram_iocfg()
655 writel(grp->grp_addds, &mx6_grp_iomux->grp_addds); in mx6ul_dram_iocfg()
658 writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset); in mx6ul_dram_iocfg()
659 writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2); in mx6ul_dram_iocfg()
660 writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0); in mx6ul_dram_iocfg()
661 writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1); in mx6ul_dram_iocfg()
662 writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds); in mx6ul_dram_iocfg()
665 writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl); in mx6ul_dram_iocfg()
666 writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0); in mx6ul_dram_iocfg()
667 writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1); in mx6ul_dram_iocfg()
670 writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode); in mx6ul_dram_iocfg()
671 writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds); in mx6ul_dram_iocfg()
672 writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds); in mx6ul_dram_iocfg()
673 writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0); in mx6ul_dram_iocfg()
674 writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1); in mx6ul_dram_iocfg()
690 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type; in mx6sl_dram_iocfg()
691 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke; in mx6sl_dram_iocfg()
694 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0; in mx6sl_dram_iocfg()
697 mx6_ddr_iomux->dram_cas = ddr->dram_cas; in mx6sl_dram_iocfg()
698 mx6_ddr_iomux->dram_ras = ddr->dram_ras; in mx6sl_dram_iocfg()
699 mx6_grp_iomux->grp_addds = grp->grp_addds; in mx6sl_dram_iocfg()
702 mx6_ddr_iomux->dram_reset = ddr->dram_reset; in mx6sl_dram_iocfg()
703 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2; in mx6sl_dram_iocfg()
704 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds; in mx6sl_dram_iocfg()
707 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl; in mx6sl_dram_iocfg()
708 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0; in mx6sl_dram_iocfg()
709 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1; in mx6sl_dram_iocfg()
711 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2; in mx6sl_dram_iocfg()
712 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3; in mx6sl_dram_iocfg()
716 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode; in mx6sl_dram_iocfg()
717 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds; in mx6sl_dram_iocfg()
718 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds; in mx6sl_dram_iocfg()
720 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds; in mx6sl_dram_iocfg()
721 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds; in mx6sl_dram_iocfg()
724 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0; in mx6sl_dram_iocfg()
725 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1; in mx6sl_dram_iocfg()
727 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2; in mx6sl_dram_iocfg()
728 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3; in mx6sl_dram_iocfg()
746 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type; in mx6dq_dram_iocfg()
747 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke; in mx6dq_dram_iocfg()
750 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0; in mx6dq_dram_iocfg()
751 mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1; in mx6dq_dram_iocfg()
754 mx6_ddr_iomux->dram_cas = ddr->dram_cas; in mx6dq_dram_iocfg()
755 mx6_ddr_iomux->dram_ras = ddr->dram_ras; in mx6dq_dram_iocfg()
756 mx6_grp_iomux->grp_addds = grp->grp_addds; in mx6dq_dram_iocfg()
759 mx6_ddr_iomux->dram_reset = ddr->dram_reset; in mx6dq_dram_iocfg()
760 mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0; in mx6dq_dram_iocfg()
761 mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1; in mx6dq_dram_iocfg()
762 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2; in mx6dq_dram_iocfg()
763 mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0; in mx6dq_dram_iocfg()
764 mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1; in mx6dq_dram_iocfg()
765 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds; in mx6dq_dram_iocfg()
768 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl; in mx6dq_dram_iocfg()
769 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0; in mx6dq_dram_iocfg()
770 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1; in mx6dq_dram_iocfg()
772 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2; in mx6dq_dram_iocfg()
773 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3; in mx6dq_dram_iocfg()
776 mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4; in mx6dq_dram_iocfg()
777 mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5; in mx6dq_dram_iocfg()
778 mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6; in mx6dq_dram_iocfg()
779 mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7; in mx6dq_dram_iocfg()
783 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode; in mx6dq_dram_iocfg()
784 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds; in mx6dq_dram_iocfg()
785 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds; in mx6dq_dram_iocfg()
787 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds; in mx6dq_dram_iocfg()
788 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds; in mx6dq_dram_iocfg()
791 mx6_grp_iomux->grp_b4ds = grp->grp_b4ds; in mx6dq_dram_iocfg()
792 mx6_grp_iomux->grp_b5ds = grp->grp_b5ds; in mx6dq_dram_iocfg()
793 mx6_grp_iomux->grp_b6ds = grp->grp_b6ds; in mx6dq_dram_iocfg()
794 mx6_grp_iomux->grp_b7ds = grp->grp_b7ds; in mx6dq_dram_iocfg()
796 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0; in mx6dq_dram_iocfg()
797 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1; in mx6dq_dram_iocfg()
799 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2; in mx6dq_dram_iocfg()
800 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3; in mx6dq_dram_iocfg()
803 mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4; in mx6dq_dram_iocfg()
804 mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5; in mx6dq_dram_iocfg()
805 mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6; in mx6dq_dram_iocfg()
806 mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7; in mx6dq_dram_iocfg()
824 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type; in mx6sdl_dram_iocfg()
825 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke; in mx6sdl_dram_iocfg()
828 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0; in mx6sdl_dram_iocfg()
829 mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1; in mx6sdl_dram_iocfg()
832 mx6_ddr_iomux->dram_cas = ddr->dram_cas; in mx6sdl_dram_iocfg()
833 mx6_ddr_iomux->dram_ras = ddr->dram_ras; in mx6sdl_dram_iocfg()
834 mx6_grp_iomux->grp_addds = grp->grp_addds; in mx6sdl_dram_iocfg()
837 mx6_ddr_iomux->dram_reset = ddr->dram_reset; in mx6sdl_dram_iocfg()
838 mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0; in mx6sdl_dram_iocfg()
839 mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1; in mx6sdl_dram_iocfg()
840 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2; in mx6sdl_dram_iocfg()
841 mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0; in mx6sdl_dram_iocfg()
842 mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1; in mx6sdl_dram_iocfg()
843 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds; in mx6sdl_dram_iocfg()
846 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl; in mx6sdl_dram_iocfg()
847 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0; in mx6sdl_dram_iocfg()
848 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1; in mx6sdl_dram_iocfg()
850 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2; in mx6sdl_dram_iocfg()
851 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3; in mx6sdl_dram_iocfg()
854 mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4; in mx6sdl_dram_iocfg()
855 mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5; in mx6sdl_dram_iocfg()
856 mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6; in mx6sdl_dram_iocfg()
857 mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7; in mx6sdl_dram_iocfg()
861 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode; in mx6sdl_dram_iocfg()
862 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds; in mx6sdl_dram_iocfg()
863 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds; in mx6sdl_dram_iocfg()
865 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds; in mx6sdl_dram_iocfg()
866 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds; in mx6sdl_dram_iocfg()
869 mx6_grp_iomux->grp_b4ds = grp->grp_b4ds; in mx6sdl_dram_iocfg()
870 mx6_grp_iomux->grp_b5ds = grp->grp_b5ds; in mx6sdl_dram_iocfg()
871 mx6_grp_iomux->grp_b6ds = grp->grp_b6ds; in mx6sdl_dram_iocfg()
872 mx6_grp_iomux->grp_b7ds = grp->grp_b7ds; in mx6sdl_dram_iocfg()
874 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0; in mx6sdl_dram_iocfg()
875 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1; in mx6sdl_dram_iocfg()
877 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2; in mx6sdl_dram_iocfg()
878 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3; in mx6sdl_dram_iocfg()
881 mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4; in mx6sdl_dram_iocfg()
882 mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5; in mx6sdl_dram_iocfg()
883 mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6; in mx6sdl_dram_iocfg()
884 mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7; in mx6sdl_dram_iocfg()
891 * - board-specific memory configuration
892 * - board-specific calibration data
893 * - ddr3/lpddr2 chip details
896 * 1. i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate
912 mmdc1->entry = value; \
916 * According JESD209-2B-LPDDR2: Table 103
942 * According JESD209-2B-LPDDR2: Table 103
986 if (sysinfo->dsize > 1) in mx6_lpddr2_cfg()
992 clkper = (1000 * 1000) / clock; /* pico seconds */ in mx6_lpddr2_cfg()
994 twl = lpddr2_wl(lpddr2_cfg->mem_speed) - 1; in mx6_lpddr2_cfg()
996 /* LPDDR2-S2 and LPDDR2-S4 have the same tRFC value. */ in mx6_lpddr2_cfg()
997 switch (lpddr2_cfg->density) { in mx6_lpddr2_cfg()
1001 trfc = DIV_ROUND_UP(130000, clkper) - 1; in mx6_lpddr2_cfg()
1002 txsr = DIV_ROUND_UP(140000, clkper) - 1; in mx6_lpddr2_cfg()
1005 trfc = DIV_ROUND_UP(210000, clkper) - 1; in mx6_lpddr2_cfg()
1006 txsr = DIV_ROUND_UP(220000, clkper) - 1; in mx6_lpddr2_cfg()
1018 txp = DIV_ROUND_UP(7500, clkper) - 1; in mx6_lpddr2_cfg()
1020 if (lpddr2_cfg->mem_speed == 333) in mx6_lpddr2_cfg()
1021 tfaw = DIV_ROUND_UP(60000, clkper) - 1; in mx6_lpddr2_cfg()
1023 tfaw = DIV_ROUND_UP(50000, clkper) - 1; in mx6_lpddr2_cfg()
1024 trrd = DIV_ROUND_UP(10000, clkper) - 1; in mx6_lpddr2_cfg()
1029 twr = DIV_ROUND_UP(15000, clkper) - 1; in mx6_lpddr2_cfg()
1035 tras = DIV_ROUND_UP(lpddr2_cfg->trasmin, clkper / 10) - 1; in mx6_lpddr2_cfg()
1037 trcd_lp = DIV_ROUND_UP(lpddr2_cfg->trcd_lp, clkper / 10) - 1; in mx6_lpddr2_cfg()
1038 trc_lp = DIV_ROUND_UP(lpddr2_cfg->trasmin + lpddr2_cfg->trppb_lp, in mx6_lpddr2_cfg()
1039 clkper / 10) - 1; in mx6_lpddr2_cfg()
1040 trppb_lp = DIV_ROUND_UP(lpddr2_cfg->trppb_lp, clkper / 10) - 1; in mx6_lpddr2_cfg()
1041 trpab_lp = DIV_ROUND_UP(lpddr2_cfg->trpab_lp, clkper / 10) - 1; in mx6_lpddr2_cfg()
1043 tcl = lpddr2_rl(lpddr2_cfg->mem_speed) - 3; in mx6_lpddr2_cfg()
1044 twtr = DIV_ROUND_UP(7500, clkper) - 1; in mx6_lpddr2_cfg()
1045 trtp = DIV_ROUND_UP(7500, clkper) - 1; in mx6_lpddr2_cfg()
1047 cs0_end = 4 * sysinfo->cs_density - 1; in mx6_lpddr2_cfg()
1050 sysinfo->cs_density, lpddr2_cfg->density); in mx6_lpddr2_cfg()
1052 debug("memspd:%d\n", lpddr2_cfg->mem_speed); in mx6_lpddr2_cfg()
1073 debug("ncs=%d\n", sysinfo->ncs); in mx6_lpddr2_cfg()
1076 * board-specific configuration: in mx6_lpddr2_cfg()
1079 mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0; in mx6_lpddr2_cfg()
1080 mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1; in mx6_lpddr2_cfg()
1081 mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0; in mx6_lpddr2_cfg()
1082 mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1; in mx6_lpddr2_cfg()
1083 mmdc0->mprddlctl = calib->p0_mprddlctl; in mx6_lpddr2_cfg()
1084 mmdc0->mpwrdlctl = calib->p0_mpwrdlctl; in mx6_lpddr2_cfg()
1085 mmdc0->mpzqlp2ctl = calib->mpzqlp2ctl; in mx6_lpddr2_cfg()
1087 /* Read data DQ Byte0-3 delay */ in mx6_lpddr2_cfg()
1088 mmdc0->mprddqby0dl = 0x33333333; in mx6_lpddr2_cfg()
1089 mmdc0->mprddqby1dl = 0x33333333; in mx6_lpddr2_cfg()
1090 if (sysinfo->dsize > 0) { in mx6_lpddr2_cfg()
1091 mmdc0->mprddqby2dl = 0x33333333; in mx6_lpddr2_cfg()
1092 mmdc0->mprddqby3dl = 0x33333333; in mx6_lpddr2_cfg()
1095 /* Write data DQ Byte0-3 delay */ in mx6_lpddr2_cfg()
1096 mmdc0->mpwrdqby0dl = 0xf3333333; in mx6_lpddr2_cfg()
1097 mmdc0->mpwrdqby1dl = 0xf3333333; in mx6_lpddr2_cfg()
1098 if (sysinfo->dsize > 0) { in mx6_lpddr2_cfg()
1099 mmdc0->mpwrdqby2dl = 0xf3333333; in mx6_lpddr2_cfg()
1100 mmdc0->mpwrdqby3dl = 0xf3333333; in mx6_lpddr2_cfg()
1107 mmdc0->mpodtctrl = 0; in mx6_lpddr2_cfg()
1110 val = (1 << 11); /* Force measurement on delay-lines */ in mx6_lpddr2_cfg()
1111 mmdc0->mpmur0 = val; in mx6_lpddr2_cfg()
1114 mmdc0->mdscr = (u32)(1 << 15); /* config request */ in mx6_lpddr2_cfg()
1117 mmdc0->mdcfg0 = (trfc << 24) | (txsr << 16) | (txp << 13) | in mx6_lpddr2_cfg()
1119 mmdc0->mdcfg1 = (tras << 16) | (twr << 9) | (tmrd << 5) | twl; in mx6_lpddr2_cfg()
1120 mmdc0->mdcfg2 = (trtp << 6) | (twtr << 3) | trrd; in mx6_lpddr2_cfg()
1121 mmdc0->mdcfg3lp = (trc_lp << 16) | (trcd_lp << 8) | in mx6_lpddr2_cfg()
1123 mmdc0->mdotc = 0; in mx6_lpddr2_cfg()
1125 mmdc0->mdasp = cs0_end; /* CS addressing */ in mx6_lpddr2_cfg()
1128 mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) | in mx6_lpddr2_cfg()
1129 (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) | in mx6_lpddr2_cfg()
1130 (sysinfo->ralat << 6) | (1 << 3); in mx6_lpddr2_cfg()
1133 mmdc0->mdor = (sysinfo->sde_to_rst << 8) | in mx6_lpddr2_cfg()
1134 (sysinfo->rst_to_cke << 0); in mx6_lpddr2_cfg()
1137 coladdr = lpddr2_cfg->coladdr; in mx6_lpddr2_cfg()
1138 if (lpddr2_cfg->coladdr == 8) /* 8-bit COL is 0x3 */ in mx6_lpddr2_cfg()
1140 else if (lpddr2_cfg->coladdr == 12) /* 12-bit COL is 0x4 */ in mx6_lpddr2_cfg()
1142 mmdc0->mdctl = (lpddr2_cfg->rowaddr - 11) << 24 | /* ROW */ in mx6_lpddr2_cfg()
1143 (coladdr - 9) << 20 | /* COL */ in mx6_lpddr2_cfg()
1145 (sysinfo->dsize << 16); /* DDR data bus size */ in mx6_lpddr2_cfg()
1148 val = 0xa1390003; /* one-time HW ZQ calib */ in mx6_lpddr2_cfg()
1149 mmdc0->mpzqhwctrl = val; in mx6_lpddr2_cfg()
1152 mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */ in mx6_lpddr2_cfg()
1153 ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */ in mx6_lpddr2_cfg()
1156 for (cs = 0; cs < sysinfo->ncs; cs++) { in mx6_lpddr2_cfg()
1158 mmdc0->mdscr = MR(63, 0, 3, cs); in mx6_lpddr2_cfg()
1163 mmdc0->mdscr = MR(val, 0, 3, cs); in mx6_lpddr2_cfg()
1166 mmdc0->mdscr = MR(val, 0, 3, cs); in mx6_lpddr2_cfg()
1169 mmdc0->mdscr = MR(val, 0, 3, cs); in mx6_lpddr2_cfg()
1172 mmdc0->mdscr = MR(val, 0, 3, cs); in mx6_lpddr2_cfg()
1175 /* Step 10: Power down control and self-refresh */ in mx6_lpddr2_cfg()
1176 mmdc0->mdpdc = (tcke & 0x7) << 16 | in mx6_lpddr2_cfg()
1182 mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */ in mx6_lpddr2_cfg()
1184 /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */ in mx6_lpddr2_cfg()
1186 mmdc0->mpzqhwctrl = val; in mx6_lpddr2_cfg()
1189 mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11); in mx6_lpddr2_cfg()
1191 /* Step 13: Deassert config request - init complete */ in mx6_lpddr2_cfg()
1192 mmdc0->mdscr = 0x00000000; in mx6_lpddr2_cfg()
1194 /* wait for auto-ZQ calibration to complete */ in mx6_lpddr2_cfg()
1215 u16 mem_speed = ddr3_cfg->mem_speed; in mx6_ddr3_cfg()
1246 clkper = (1000 * 1000) / clock; /* pico seconds */ in mx6_ddr3_cfg()
1251 switch (ddr3_cfg->density) { in mx6_ddr3_cfg()
1253 trfc = DIV_ROUND_UP(110000, clkper) - 1; in mx6_ddr3_cfg()
1254 txs = DIV_ROUND_UP(120000, clkper) - 1; in mx6_ddr3_cfg()
1257 trfc = DIV_ROUND_UP(160000, clkper) - 1; in mx6_ddr3_cfg()
1258 txs = DIV_ROUND_UP(170000, clkper) - 1; in mx6_ddr3_cfg()
1261 trfc = DIV_ROUND_UP(260000, clkper) - 1; in mx6_ddr3_cfg()
1262 txs = DIV_ROUND_UP(270000, clkper) - 1; in mx6_ddr3_cfg()
1265 trfc = DIV_ROUND_UP(350000, clkper) - 1; in mx6_ddr3_cfg()
1266 txs = DIV_ROUND_UP(360000, clkper) - 1; in mx6_ddr3_cfg()
1278 txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1; in mx6_ddr3_cfg()
1279 tcke = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1; in mx6_ddr3_cfg()
1280 if (ddr3_cfg->pagesz == 1) { in mx6_ddr3_cfg()
1281 tfaw = DIV_ROUND_UP(40000, clkper) - 1; in mx6_ddr3_cfg()
1282 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1; in mx6_ddr3_cfg()
1284 tfaw = DIV_ROUND_UP(50000, clkper) - 1; in mx6_ddr3_cfg()
1285 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1; in mx6_ddr3_cfg()
1289 txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1; in mx6_ddr3_cfg()
1290 tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1; in mx6_ddr3_cfg()
1291 if (ddr3_cfg->pagesz == 1) { in mx6_ddr3_cfg()
1292 tfaw = DIV_ROUND_UP(37500, clkper) - 1; in mx6_ddr3_cfg()
1293 trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1; in mx6_ddr3_cfg()
1295 tfaw = DIV_ROUND_UP(50000, clkper) - 1; in mx6_ddr3_cfg()
1296 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1; in mx6_ddr3_cfg()
1304 txpdll = DIV_ROUND_UP(max(10 * clkper, 24000), clkper) - 1; in mx6_ddr3_cfg()
1306 taonpd = DIV_ROUND_UP(2000, clkper) - 1; in mx6_ddr3_cfg()
1309 twr = DIV_ROUND_UP(15000, clkper) - 1; in mx6_ddr3_cfg()
1310 tmrd = DIV_ROUND_UP(max(12 * clkper, 15000), clkper) - 1; in mx6_ddr3_cfg()
1311 trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1; in mx6_ddr3_cfg()
1312 tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1; in mx6_ddr3_cfg()
1313 tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3; in mx6_ddr3_cfg()
1314 trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1; in mx6_ddr3_cfg()
1315 twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1; in mx6_ddr3_cfg()
1318 cs0_end = 4 * sysinfo->cs_density - 1; in mx6_ddr3_cfg()
1321 sysinfo->cs_density, ddr3_cfg->density); in mx6_ddr3_cfg()
1351 debug("ncs=%d\n", sysinfo->ncs); in mx6_ddr3_cfg()
1352 debug("Rtt_wr=%d\n", sysinfo->rtt_wr); in mx6_ddr3_cfg()
1353 debug("Rtt_nom=%d\n", sysinfo->rtt_nom); in mx6_ddr3_cfg()
1354 debug("SRT=%d\n", ddr3_cfg->SRT); in mx6_ddr3_cfg()
1358 * board-specific configuration: in mx6_ddr3_cfg()
1363 mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0; in mx6_ddr3_cfg()
1364 mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1; in mx6_ddr3_cfg()
1365 mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0; in mx6_ddr3_cfg()
1366 mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1; in mx6_ddr3_cfg()
1367 mmdc0->mprddlctl = calib->p0_mprddlctl; in mx6_ddr3_cfg()
1368 mmdc0->mpwrdlctl = calib->p0_mpwrdlctl; in mx6_ddr3_cfg()
1369 if (sysinfo->dsize > 1) { in mx6_ddr3_cfg()
1370 MMDC1(mpwldectrl0, calib->p1_mpwldectrl0); in mx6_ddr3_cfg()
1371 MMDC1(mpwldectrl1, calib->p1_mpwldectrl1); in mx6_ddr3_cfg()
1372 MMDC1(mpdgctrl0, calib->p1_mpdgctrl0); in mx6_ddr3_cfg()
1373 MMDC1(mpdgctrl1, calib->p1_mpdgctrl1); in mx6_ddr3_cfg()
1374 MMDC1(mprddlctl, calib->p1_mprddlctl); in mx6_ddr3_cfg()
1375 MMDC1(mpwrdlctl, calib->p1_mpwrdlctl); in mx6_ddr3_cfg()
1378 /* Read data DQ Byte0-3 delay */ in mx6_ddr3_cfg()
1379 mmdc0->mprddqby0dl = 0x33333333; in mx6_ddr3_cfg()
1380 mmdc0->mprddqby1dl = 0x33333333; in mx6_ddr3_cfg()
1381 if (sysinfo->dsize > 0) { in mx6_ddr3_cfg()
1382 mmdc0->mprddqby2dl = 0x33333333; in mx6_ddr3_cfg()
1383 mmdc0->mprddqby3dl = 0x33333333; in mx6_ddr3_cfg()
1386 if (sysinfo->dsize > 1) { in mx6_ddr3_cfg()
1394 val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227; in mx6_ddr3_cfg()
1395 mmdc0->mpodtctrl = val; in mx6_ddr3_cfg()
1396 if (sysinfo->dsize > 1) in mx6_ddr3_cfg()
1400 val = (1 << 11); /* Force measurement on delay-lines */ in mx6_ddr3_cfg()
1401 mmdc0->mpmur0 = val; in mx6_ddr3_cfg()
1402 if (sysinfo->dsize > 1) in mx6_ddr3_cfg()
1406 mmdc0->mdscr = (u32)(1 << 15); /* config request */ in mx6_ddr3_cfg()
1409 mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) | in mx6_ddr3_cfg()
1411 mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) | in mx6_ddr3_cfg()
1414 mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd; in mx6_ddr3_cfg()
1415 mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) | in mx6_ddr3_cfg()
1417 mmdc0->mdasp = cs0_end; /* CS addressing */ in mx6_ddr3_cfg()
1420 mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) | in mx6_ddr3_cfg()
1421 (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) | in mx6_ddr3_cfg()
1422 (sysinfo->ralat << 6); in mx6_ddr3_cfg()
1425 mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) | in mx6_ddr3_cfg()
1426 (sysinfo->rst_to_cke << 0); in mx6_ddr3_cfg()
1429 coladdr = ddr3_cfg->coladdr; in mx6_ddr3_cfg()
1430 if (ddr3_cfg->coladdr == 8) /* 8-bit COL is 0x3 */ in mx6_ddr3_cfg()
1432 else if (ddr3_cfg->coladdr == 12) /* 12-bit COL is 0x4 */ in mx6_ddr3_cfg()
1434 mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */ in mx6_ddr3_cfg()
1435 (coladdr - 9) << 20 | /* COL */ in mx6_ddr3_cfg()
1437 (sysinfo->dsize << 16); /* DDR data bus size */ in mx6_ddr3_cfg()
1440 val = 0xa1390001; /* one-time HW ZQ calib */ in mx6_ddr3_cfg()
1441 mmdc0->mpzqhwctrl = val; in mx6_ddr3_cfg()
1442 if (sysinfo->dsize > 1) in mx6_ddr3_cfg()
1446 mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */ in mx6_ddr3_cfg()
1447 ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */ in mx6_ddr3_cfg()
1450 for (cs = 0; cs < sysinfo->ncs; cs++) { in mx6_ddr3_cfg()
1452 val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 | in mx6_ddr3_cfg()
1453 ((tcwl - 3) & 3) << 3; in mx6_ddr3_cfg()
1455 mmdc0->mdscr = MR(val, 2, 3, cs); in mx6_ddr3_cfg()
1458 mmdc0->mdscr = MR(0, 3, 3, cs); in mx6_ddr3_cfg()
1460 val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 | in mx6_ddr3_cfg()
1461 ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6; in mx6_ddr3_cfg()
1463 mmdc0->mdscr = MR(val, 1, 3, cs); in mx6_ddr3_cfg()
1465 val = ((tcl - 1) << 4) | /* CAS */ in mx6_ddr3_cfg()
1467 ((twr - 3) << 9) | /* Write Recovery */ in mx6_ddr3_cfg()
1468 (sysinfo->pd_fast_exit << 12); /* Precharge PD PLL on */ in mx6_ddr3_cfg()
1470 mmdc0->mdscr = MR(val, 0, 3, cs); in mx6_ddr3_cfg()
1473 mmdc0->mdscr = MR(val, 0, 4, cs); in mx6_ddr3_cfg()
1476 /* Step 10: Power down control and self-refresh */ in mx6_ddr3_cfg()
1477 mmdc0->mdpdc = (tcke & 0x7) << 16 | in mx6_ddr3_cfg()
1483 if (!sysinfo->pd_fast_exit) in mx6_ddr3_cfg()
1484 mmdc0->mdpdc |= (1 << 7); /* SLOW_PD */ in mx6_ddr3_cfg()
1485 mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */ in mx6_ddr3_cfg()
1487 /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */ in mx6_ddr3_cfg()
1489 mmdc0->mpzqhwctrl = val; in mx6_ddr3_cfg()
1490 if (sysinfo->dsize > 1) in mx6_ddr3_cfg()
1494 mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11); in mx6_ddr3_cfg()
1496 /* Step 13: Deassert config request - init complete */ in mx6_ddr3_cfg()
1497 mmdc0->mdscr = 0x00000000; in mx6_ddr3_cfg()
1499 /* wait for auto-ZQ calibration to complete */ in mx6_ddr3_cfg()
1509 calib->p0_mpwldectrl0 = readl(&mmdc0->mpwldectrl0); in mmdc_read_calibration()
1510 calib->p0_mpwldectrl1 = readl(&mmdc0->mpwldectrl1); in mmdc_read_calibration()
1511 calib->p0_mpdgctrl0 = readl(&mmdc0->mpdgctrl0); in mmdc_read_calibration()
1512 calib->p0_mpdgctrl1 = readl(&mmdc0->mpdgctrl1); in mmdc_read_calibration()
1513 calib->p0_mprddlctl = readl(&mmdc0->mprddlctl); in mmdc_read_calibration()
1514 calib->p0_mpwrdlctl = readl(&mmdc0->mpwrdlctl); in mmdc_read_calibration()
1516 if (sysinfo->dsize == 2) { in mmdc_read_calibration()
1517 calib->p1_mpwldectrl0 = readl(&mmdc1->mpwldectrl0); in mmdc_read_calibration()
1518 calib->p1_mpwldectrl1 = readl(&mmdc1->mpwldectrl1); in mmdc_read_calibration()
1519 calib->p1_mpdgctrl0 = readl(&mmdc1->mpdgctrl0); in mmdc_read_calibration()
1520 calib->p1_mpdgctrl1 = readl(&mmdc1->mpdgctrl1); in mmdc_read_calibration()
1521 calib->p1_mprddlctl = readl(&mmdc1->mprddlctl); in mmdc_read_calibration()
1522 calib->p1_mpwrdlctl = readl(&mmdc1->mpwrdlctl); in mmdc_read_calibration()
1530 if (sysinfo->ddr_type == DDR_TYPE_DDR3) { in mx6_dram_cfg()
1532 } else if (sysinfo->ddr_type == DDR_TYPE_LPDDR2) { in mx6_dram_cfg()