Lines Matching full:lpddr2

893  *  - ddr3/lpddr2 chip details
900  * 2. i.Mx6SL LPDDR2 Script Aid spreadsheet V0.04 designed to generate MMDC
916  * According JESD209-2B-LPDDR2: Table 103
942  * According JESD209-2B-LPDDR2: Table 103
996 	/* LPDDR2-S2 and LPDDR2-S4 have the same tRFC value. */  in mx6_lpddr2_cfg()
1016 	 * txpdll, txpr, taonpd and taofpd are not relevant in LPDDR2 mode,  in mx6_lpddr2_cfg()
1026 	/* tckesr for LPDDR2 */  in mx6_lpddr2_cfg()
1036 	/* LPDDR2 mode use tRCD_LP filed in MDCFG3. */  in mx6_lpddr2_cfg()
1042 	/* To LPDDR2, CL in MDCFG0 refers to RL */  in mx6_lpddr2_cfg()
1104 	 * In LPDDR2 mode this register should be cleared,  in mx6_lpddr2_cfg()
1144 			(0 << 19) |	/* Burst Length = 4 for LPDDR2 */  in mx6_lpddr2_cfg()
1155 	/* Step 8: Write Mode Registers to Init LPDDR2 devices */  in mx6_lpddr2_cfg()