Lines Matching +full:0 +full:x7000
24 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0); in reset_read_data_fifos()
27 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0); in reset_read_data_fifos()
41 writel(0x04008050, &mmdc0->mdscr); in precharge_all()
42 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0); in precharge_all()
46 writel(0x04008058, &mmdc0->mdscr); in precharge_all()
47 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0); in precharge_all()
56 writel(0x800, &mmdc0->mpmur0); in force_delay_measurement()
57 if (bus_size == 0x2) in force_delay_measurement()
58 writel(0x800, &mmdc1->mpmur0); in force_delay_measurement()
67 * (HW_DG_LOWx + HW_DG_UPx)/2 to reflecting (HW_DG_UPx - 0x80) in modify_dg_result()
71 val_ctrl &= 0xf0000000; in modify_dg_result()
73 dg_tmp_val = ((readl(reg_st0) & 0x07ff0000) >> 16) - 0xc0; in modify_dg_result()
74 dg_dl_abs_offset = dg_tmp_val & 0x7f; in modify_dg_result()
75 dg_hc_del = (dg_tmp_val & 0x780) << 1; in modify_dg_result()
79 dg_tmp_val = ((readl(reg_st1) & 0x07ff0000) >> 16) - 0xc0; in modify_dg_result()
80 dg_dl_abs_offset = dg_tmp_val & 0x7f; in modify_dg_result()
81 dg_hc_del = (dg_tmp_val & 0x780) << 1; in modify_dg_result()
93 u32 errors = 0; in mmdc_do_write_level_calibration()
94 u32 ldectrl[4] = {0}; in mmdc_do_write_level_calibration()
95 u32 ddr_mr1 = 0x4; in mmdc_do_write_level_calibration()
102 ldectrl[0] = readl(&mmdc0->mpwldectrl0); in mmdc_do_write_level_calibration()
110 clrbits_le32(&mmdc0->mdpdc, 0xff00); in mmdc_do_write_level_calibration()
113 setbits_le32(&mmdc0->mapsr, 0x1); in mmdc_do_write_level_calibration()
122 writel(0x0000C000, &mmdc0->mdref); in mmdc_do_write_level_calibration()
124 writel(zq_val & ~0x3, &mmdc0->mpzqhwctrl); in mmdc_do_write_level_calibration()
135 * Bits[31:16] MR1 value (0x0080 write leveling enable) in mmdc_do_write_level_calibration()
138 * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming in mmdc_do_write_level_calibration()
140 writel(0x00808231, &mmdc0->mdscr); in mmdc_do_write_level_calibration()
143 writel(0x00000001, &mmdc0->mpwlgcr); in mmdc_do_write_level_calibration()
149 wait_for_bit_le32(&mmdc0->mpwlgcr, 1 << 0, 0, 100, 0); in mmdc_do_write_level_calibration()
155 if (readl(&mmdc0->mpwlgcr) & 0x00000F00) in mmdc_do_write_level_calibration()
158 if (readl(&mmdc1->mpwlgcr) & 0x00000F00) in mmdc_do_write_level_calibration()
161 debug("Ending write leveling calibration. Error mask: 0x%x\n", errors); in mmdc_do_write_level_calibration()
164 if ((readl(&mmdc0->mpwldectrl0) == 0x001F001F) && in mmdc_do_write_level_calibration()
165 (readl(&mmdc0->mpwldectrl1) == 0x001F001F) && in mmdc_do_write_level_calibration()
167 ((readl(&mmdc1->mpwldectrl0) == 0x001F001F) && in mmdc_do_write_level_calibration()
168 (readl(&mmdc1->mpwldectrl1) == 0x001F001F)))) { in mmdc_do_write_level_calibration()
170 writel(ldectrl[0], &mmdc0->mpwldectrl0); in mmdc_do_write_level_calibration()
186 * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming in mmdc_do_write_level_calibration()
188 writel((ddr_mr1 << 16) + 0x8031, &mmdc0->mdscr); in mmdc_do_write_level_calibration()
194 debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n", in mmdc_do_write_level_calibration()
196 debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n", in mmdc_do_write_level_calibration()
199 debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n", in mmdc_do_write_level_calibration()
201 debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n", in mmdc_do_write_level_calibration()
214 setbits_le32(&mmdc0->mdpdc, 0x00005500); in mmdc_do_write_level_calibration()
217 clrbits_le32(&mmdc0->mapsr, 0x1); in mmdc_do_write_level_calibration()
220 writel(0, &mmdc0->mdscr); in mmdc_do_write_level_calibration()
237 u32 pddword = 0x00ffff00; /* best so far, place into MPPDCMPR1 */ in mmdc_do_dqs_calibration()
238 u32 errors = 0; in mmdc_do_dqs_calibration()
239 u32 initdelay = 0x40404040; in mmdc_do_dqs_calibration()
242 cs0_enable_initial = readl(&mmdc0->mdctl) & 0x80000000; in mmdc_do_dqs_calibration()
243 cs1_enable_initial = readl(&mmdc0->mdctl) & 0x40000000; in mmdc_do_dqs_calibration()
246 clrbits_le32(&mmdc0->mdpdc, 0xff00); in mmdc_do_dqs_calibration()
249 setbits_le32(&mmdc0->mapsr, 0x1); in mmdc_do_dqs_calibration()
252 setbits_le32(&mx6_ddr_iomux->dram_sdqs0, 0x7000); in mmdc_do_dqs_calibration()
253 setbits_le32(&mx6_ddr_iomux->dram_sdqs1, 0x7000); in mmdc_do_dqs_calibration()
254 setbits_le32(&mx6_ddr_iomux->dram_sdqs2, 0x7000); in mmdc_do_dqs_calibration()
255 setbits_le32(&mx6_ddr_iomux->dram_sdqs3, 0x7000); in mmdc_do_dqs_calibration()
256 setbits_le32(&mx6_ddr_iomux->dram_sdqs4, 0x7000); in mmdc_do_dqs_calibration()
257 setbits_le32(&mx6_ddr_iomux->dram_sdqs5, 0x7000); in mmdc_do_dqs_calibration()
258 setbits_le32(&mx6_ddr_iomux->dram_sdqs6, 0x7000); in mmdc_do_dqs_calibration()
259 setbits_le32(&mx6_ddr_iomux->dram_sdqs7, 0x7000); in mmdc_do_dqs_calibration()
269 writel(0x0000c000, &mmdc0->mdref); in mmdc_do_dqs_calibration()
272 * Per the ref manual, issue one refresh cycle MDSCR[CMD]= 0x2, in mmdc_do_dqs_calibration()
276 writel(0x00008020, &mmdc0->mdscr); in mmdc_do_dqs_calibration()
278 writel(0x00008028, &mmdc0->mdscr); in mmdc_do_dqs_calibration()
281 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0); in mmdc_do_dqs_calibration()
292 if ((readl(&mmdc0->mdmisc) & 0x00100000) == 0) in mmdc_do_dqs_calibration()
301 cs0_enable = readl(&mmdc0->mdctl) & 0x80000000; in mmdc_do_dqs_calibration()
302 cs1_enable = readl(&mmdc0->mdctl) & 0x40000000; in mmdc_do_dqs_calibration()
311 * the bit SW_DUMMY_WR (bit 0) in the MPSWDAR0 and then poll in mmdc_do_dqs_calibration()
315 wait_for_bit_le32(&mmdc0->mpswdar0, 1 << 0, 0, 100, 0); in mmdc_do_dqs_calibration()
322 if (sysinfo->dsize == 0x2) in mmdc_do_dqs_calibration()
361 /* Poll for completion. MPDGCTRL0[HW_DG_EN] should be 0 */ in mmdc_do_dqs_calibration()
362 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0); in mmdc_do_dqs_calibration()
369 if (readl(&mmdc0->mpdgctrl0) & 0x00001000) in mmdc_do_dqs_calibration()
372 if ((sysinfo->dsize == 0x2) && (readl(&mmdc1->mpdgctrl0) & 0x00001000)) in mmdc_do_dqs_calibration()
383 * reflecting (HW_DG_UPx - 0x80) in mmdc_do_dqs_calibration()
389 if (sysinfo->dsize == 0x2) { in mmdc_do_dqs_calibration()
395 debug("Ending Read DQS Gating calibration. Error mask: 0x%x\n", errors); in mmdc_do_dqs_calibration()
418 writel(0x00000030, &mmdc0->mprddlhwctl); in mmdc_do_dqs_calibration()
423 * setting MPRDDLHWCTL[HW_RD_DL_EN] = 0. Also, ensure that in mmdc_do_dqs_calibration()
426 wait_for_bit_le32(&mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0); in mmdc_do_dqs_calibration()
429 if (readl(&mmdc0->mprddlhwctl) & 0x0000000f) in mmdc_do_dqs_calibration()
432 if ((sysinfo->dsize == 0x2) && in mmdc_do_dqs_calibration()
433 (readl(&mmdc1->mprddlhwctl) & 0x0000000f)) in mmdc_do_dqs_calibration()
436 debug("Ending Read Delay calibration. Error mask: 0x%x\n", errors); in mmdc_do_dqs_calibration()
459 if (sysinfo->dsize == 0x2) in mmdc_do_dqs_calibration()
472 writel(0x00000030, &mmdc0->mpwrdlhwctl); in mmdc_do_dqs_calibration()
477 * by setting MPWRDLHWCTL[HW_WR_DL_EN] = 0. in mmdc_do_dqs_calibration()
480 wait_for_bit_le32(&mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0); in mmdc_do_dqs_calibration()
483 if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f) in mmdc_do_dqs_calibration()
486 if ((sysinfo->dsize == 0x2) && in mmdc_do_dqs_calibration()
487 (readl(&mmdc1->mpwrdlhwctl) & 0x0000000f)) in mmdc_do_dqs_calibration()
490 debug("Ending Write Delay calibration. Error mask: 0x%x\n", errors); in mmdc_do_dqs_calibration()
495 setbits_le32(&mmdc0->mdpdc, 0x00005500); in mmdc_do_dqs_calibration()
498 clrbits_le32(&mmdc0->mapsr, 0x1); in mmdc_do_dqs_calibration()
504 clrbits_le32(&mx6_ddr_iomux->dram_sdqs0, 0x7000); in mmdc_do_dqs_calibration()
505 clrbits_le32(&mx6_ddr_iomux->dram_sdqs1, 0x7000); in mmdc_do_dqs_calibration()
506 clrbits_le32(&mx6_ddr_iomux->dram_sdqs2, 0x7000); in mmdc_do_dqs_calibration()
507 clrbits_le32(&mx6_ddr_iomux->dram_sdqs3, 0x7000); in mmdc_do_dqs_calibration()
508 clrbits_le32(&mx6_ddr_iomux->dram_sdqs4, 0x7000); in mmdc_do_dqs_calibration()
509 clrbits_le32(&mx6_ddr_iomux->dram_sdqs5, 0x7000); in mmdc_do_dqs_calibration()
510 clrbits_le32(&mx6_ddr_iomux->dram_sdqs6, 0x7000); in mmdc_do_dqs_calibration()
511 clrbits_le32(&mx6_ddr_iomux->dram_sdqs7, 0x7000); in mmdc_do_dqs_calibration()
526 writel(0x0, &mmdc0->mdscr); /* CS0 */ in mmdc_do_dqs_calibration()
529 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 0, 100, 0); in mmdc_do_dqs_calibration()
537 debug("\tMPDGCTRL0 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl0)); in mmdc_do_dqs_calibration()
538 debug("\tMPDGCTRL1 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl1)); in mmdc_do_dqs_calibration()
540 debug("\tMPDGCTRL0 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl0)); in mmdc_do_dqs_calibration()
541 debug("\tMPDGCTRL1 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl1)); in mmdc_do_dqs_calibration()
544 debug("\tMPRDDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mprddlctl)); in mmdc_do_dqs_calibration()
546 debug("\tMPRDDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mprddlctl)); in mmdc_do_dqs_calibration()
548 debug("\tMPWRDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mpwrdlctl)); in mmdc_do_dqs_calibration()
550 debug("\tMPWRDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mpwrdlctl)); in mmdc_do_dqs_calibration()
558 debug("\tMPDGHWST0 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst0)); in mmdc_do_dqs_calibration()
559 debug("\tMPDGHWST1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst1)); in mmdc_do_dqs_calibration()
560 debug("\tMPDGHWST2 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst2)); in mmdc_do_dqs_calibration()
561 debug("\tMPDGHWST3 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst3)); in mmdc_do_dqs_calibration()
563 debug("\tMPDGHWST0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst0)); in mmdc_do_dqs_calibration()
564 debug("\tMPDGHWST1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst1)); in mmdc_do_dqs_calibration()
565 debug("\tMPDGHWST2 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst2)); in mmdc_do_dqs_calibration()
566 debug("\tMPDGHWST3 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst3)); in mmdc_do_dqs_calibration()
569 debug("Final do_dqs_calibration error mask: 0x%x\n", errors); in mmdc_do_dqs_calibration()
913 } while (0)
938 return 0; in lpddr2_wl()
966 return 0; in lpddr2_rl()
1017 * set them to 0. */ in mx6_lpddr2_cfg()
1088 mmdc0->mprddqby0dl = 0x33333333; in mx6_lpddr2_cfg()
1089 mmdc0->mprddqby1dl = 0x33333333; in mx6_lpddr2_cfg()
1090 if (sysinfo->dsize > 0) { in mx6_lpddr2_cfg()
1091 mmdc0->mprddqby2dl = 0x33333333; in mx6_lpddr2_cfg()
1092 mmdc0->mprddqby3dl = 0x33333333; in mx6_lpddr2_cfg()
1096 mmdc0->mpwrdqby0dl = 0xf3333333; in mx6_lpddr2_cfg()
1097 mmdc0->mpwrdqby1dl = 0xf3333333; in mx6_lpddr2_cfg()
1098 if (sysinfo->dsize > 0) { in mx6_lpddr2_cfg()
1099 mmdc0->mpwrdqby2dl = 0xf3333333; in mx6_lpddr2_cfg()
1100 mmdc0->mpwrdqby3dl = 0xf3333333; in mx6_lpddr2_cfg()
1107 mmdc0->mpodtctrl = 0; in mx6_lpddr2_cfg()
1123 mmdc0->mdotc = 0; in mx6_lpddr2_cfg()
1134 (sysinfo->rst_to_cke << 0); in mx6_lpddr2_cfg()
1138 if (lpddr2_cfg->coladdr == 8) /* 8-bit COL is 0x3 */ in mx6_lpddr2_cfg()
1140 else if (lpddr2_cfg->coladdr == 12) /* 12-bit COL is 0x4 */ in mx6_lpddr2_cfg()
1144 (0 << 19) | /* Burst Length = 4 for LPDDR2 */ in mx6_lpddr2_cfg()
1148 val = 0xa1390003; /* one-time HW ZQ calib */ in mx6_lpddr2_cfg()
1153 ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */ in mx6_lpddr2_cfg()
1156 for (cs = 0; cs < sysinfo->ncs; cs++) { in mx6_lpddr2_cfg()
1158 mmdc0->mdscr = MR(63, 0, 3, cs); in mx6_lpddr2_cfg()
1160 * 0xff is calibration command after intilization. in mx6_lpddr2_cfg()
1162 val = 0xA | (0xff << 8); in mx6_lpddr2_cfg()
1163 mmdc0->mdscr = MR(val, 0, 3, cs); in mx6_lpddr2_cfg()
1165 val = 0x1 | (0x82 << 8); in mx6_lpddr2_cfg()
1166 mmdc0->mdscr = MR(val, 0, 3, cs); in mx6_lpddr2_cfg()
1168 val = 0x2 | (0x04 << 8); in mx6_lpddr2_cfg()
1169 mmdc0->mdscr = MR(val, 0, 3, cs); in mx6_lpddr2_cfg()
1171 val = 0x3 | (0x02 << 8); in mx6_lpddr2_cfg()
1172 mmdc0->mdscr = MR(val, 0, 3, cs); in mx6_lpddr2_cfg()
1176 mmdc0->mdpdc = (tcke & 0x7) << 16 | in mx6_lpddr2_cfg()
1180 (tcksrx & 0x7) << 3 | in mx6_lpddr2_cfg()
1181 (tcksre & 0x7); in mx6_lpddr2_cfg()
1182 mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */ in mx6_lpddr2_cfg()
1185 val = 0xa1310003; in mx6_lpddr2_cfg()
1192 mmdc0->mdscr = 0x00000000; in mx6_lpddr2_cfg()
1207 u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */ in mx6_ddr3_cfg()
1210 u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */ in mx6_ddr3_cfg()
1379 mmdc0->mprddqby0dl = 0x33333333; in mx6_ddr3_cfg()
1380 mmdc0->mprddqby1dl = 0x33333333; in mx6_ddr3_cfg()
1381 if (sysinfo->dsize > 0) { in mx6_ddr3_cfg()
1382 mmdc0->mprddqby2dl = 0x33333333; in mx6_ddr3_cfg()
1383 mmdc0->mprddqby3dl = 0x33333333; in mx6_ddr3_cfg()
1387 MMDC1(mprddqby0dl, 0x33333333); in mx6_ddr3_cfg()
1388 MMDC1(mprddqby1dl, 0x33333333); in mx6_ddr3_cfg()
1389 MMDC1(mprddqby2dl, 0x33333333); in mx6_ddr3_cfg()
1390 MMDC1(mprddqby3dl, 0x33333333); in mx6_ddr3_cfg()
1394 val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227; in mx6_ddr3_cfg()
1426 (sysinfo->rst_to_cke << 0); in mx6_ddr3_cfg()
1430 if (ddr3_cfg->coladdr == 8) /* 8-bit COL is 0x3 */ in mx6_ddr3_cfg()
1432 else if (ddr3_cfg->coladdr == 12) /* 12-bit COL is 0x4 */ in mx6_ddr3_cfg()
1440 val = 0xa1390001; /* one-time HW ZQ calib */ in mx6_ddr3_cfg()
1447 ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */ in mx6_ddr3_cfg()
1450 for (cs = 0; cs < sysinfo->ncs; cs++) { in mx6_ddr3_cfg()
1454 debug("MR2 CS%d: 0x%08x\n", cs, (u32)MR(val, 2, 3, cs)); in mx6_ddr3_cfg()
1457 debug("MR3 CS%d: 0x%08x\n", cs, (u32)MR(0, 3, 3, cs)); in mx6_ddr3_cfg()
1458 mmdc0->mdscr = MR(0, 3, 3, cs); in mx6_ddr3_cfg()
1460 val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 | in mx6_ddr3_cfg()
1461 ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6; in mx6_ddr3_cfg()
1462 debug("MR1 CS%d: 0x%08x\n", cs, (u32)MR(val, 1, 3, cs)); in mx6_ddr3_cfg()
1469 debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs)); in mx6_ddr3_cfg()
1470 mmdc0->mdscr = MR(val, 0, 3, cs); in mx6_ddr3_cfg()
1473 mmdc0->mdscr = MR(val, 0, 4, cs); in mx6_ddr3_cfg()
1477 mmdc0->mdpdc = (tcke & 0x7) << 16 | in mx6_ddr3_cfg()
1481 (tcksrx & 0x7) << 3 | in mx6_ddr3_cfg()
1482 (tcksre & 0x7); in mx6_ddr3_cfg()
1485 mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */ in mx6_ddr3_cfg()
1488 val = 0xa1390003; in mx6_ddr3_cfg()
1497 mmdc0->mdscr = 0x00000000; in mx6_ddr3_cfg()