25 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;  variable
32 	reg = __raw_readl(&imx_ccm->CCGR2);  in enable_ocotp_clk()
37 	__raw_writel(reg, &imx_ccm->CCGR2);  in enable_ocotp_clk()
45 	clrbits_le32(&imx_ccm->CCGR4,  in setup_gpmi_io_clk()
53 	clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);  in setup_gpmi_io_clk()
55 	clrsetbits_le32(&imx_ccm->cs2cdr,  in setup_gpmi_io_clk()
61 	setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);  in setup_gpmi_io_clk()
63 	clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);  in setup_gpmi_io_clk()
65 	clrsetbits_le32(&imx_ccm->cs2cdr,  in setup_gpmi_io_clk()
71 	setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);  in setup_gpmi_io_clk()
73 	setbits_le32(&imx_ccm->CCGR4,  in setup_gpmi_io_clk()
86 	reg = __raw_readl(&imx_ccm->CCGR6);  in enable_usboh3_clk()
91 	__raw_writel(reg, &imx_ccm->CCGR6);  in enable_usboh3_clk()
102 		addr = &imx_ccm->CCGR0;  in enable_enet_clk()
105 		addr = &imx_ccm->CCGR3;  in enable_enet_clk()
108 		addr = &imx_ccm->CCGR1;  in enable_enet_clk()
129 		setbits_le32(&imx_ccm->CCGR5, mask);  in enable_uart_clk()
131 		clrbits_le32(&imx_ccm->CCGR5, mask);  in enable_uart_clk()
145 		setbits_le32(&imx_ccm->CCGR6, mask);  in enable_usdhc_clk()
147 		clrbits_le32(&imx_ccm->CCGR6, mask);  in enable_usdhc_clk()
167 		reg = __raw_readl(&imx_ccm->CCGR2);  in enable_i2c_clk()
172 		__raw_writel(reg, &imx_ccm->CCGR2);  in enable_i2c_clk()
178 			addr = &imx_ccm->CCGR6;  in enable_i2c_clk()
181 			addr = &imx_ccm->CCGR1;  in enable_i2c_clk()
204 	reg = __raw_readl(&imx_ccm->CCGR1);  in enable_spi_clk()
209 	__raw_writel(reg, &imx_ccm->CCGR1);  in enable_spi_clk()
218 		div = __raw_readl(&imx_ccm->analog_pll_sys);  in decode_pll()
223 		div = __raw_readl(&imx_ccm->analog_pll_528);  in decode_pll()
228 		div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);  in decode_pll()
233 		div = __raw_readl(&imx_ccm->analog_pll_enet);  in decode_pll()
238 		div = __raw_readl(&imx_ccm->analog_pll_audio);  in decode_pll()
244 		pll_num = __raw_readl(&imx_ccm->analog_pll_audio_num);  in decode_pll()
245 		pll_denom = __raw_readl(&imx_ccm->analog_pll_audio_denom);  in decode_pll()
257 		div = __raw_readl(&imx_ccm->analog_pll_video);  in decode_pll()
263 		pll_num = __raw_readl(&imx_ccm->analog_pll_video_num);  in decode_pll()
264 		pll_denom = __raw_readl(&imx_ccm->analog_pll_video_denom);  in decode_pll()
293 		div = __raw_readl(&imx_ccm->analog_pfd_528);  in mxc_get_pll_pfd()
297 		div = __raw_readl(&imx_ccm->analog_pfd_480);  in mxc_get_pll_pfd()
313 	reg = __raw_readl(&imx_ccm->cacrr);  in get_mcu_main_clk()
325 	reg = __raw_readl(&imx_ccm->cbcdr);  in get_periph_clk()
329 		reg = __raw_readl(&imx_ccm->cbcmr);  in get_periph_clk()
345 		reg = __raw_readl(&imx_ccm->cbcmr);  in get_periph_clk()
375 	reg = __raw_readl(&imx_ccm->cbcdr);  in get_ipg_clk()
386 	reg = __raw_readl(&imx_ccm->cscmr1);  in get_ipg_per_clk()
402 	reg = __raw_readl(&imx_ccm->cscdr1);  in get_uart_clk()
420 	reg = __raw_readl(&imx_ccm->cscdr2);  in get_cspi_clk()
436 	u32 cbcdr =  __raw_readl(&imx_ccm->cbcdr);  in get_axi_clk()
456 	cscmr1 =  __raw_readl(&imx_ccm->cscmr1);  in get_emi_slow_clk()
482 	u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);  in get_mmdc_ch0_clk()
483 	u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);  in get_mmdc_ch0_clk()
525 				pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2));  in get_mmdc_ch0_clk()
566 	       &imx_ccm->analog_pll_video_clr);  in enable_pll_video()
573 		       &imx_ccm->analog_pll_video_set);  in enable_pll_video()
578 		       &imx_ccm->analog_pll_video_set);  in enable_pll_video()
583 		       &imx_ccm->analog_pll_video_set);  in enable_pll_video()
591 	       &imx_ccm->analog_pll_video_num);  in enable_pll_video()
593 	       &imx_ccm->analog_pll_video_denom);  in enable_pll_video()
599 		reg = readl(&imx_ccm->analog_pll_video);  in enable_pll_video()
603 			       &imx_ccm->analog_pll_video_set);  in enable_pll_video()
639 			reg = readl(&imx_ccm->cscdr2);  in mxs_set_lcdclk()
647 		reg = readl(&imx_ccm->cscdr2);  in mxs_set_lcdclk()
717 			clrsetbits_le32(&imx_ccm->cscdr2,  in mxs_set_lcdclk()
725 			clrsetbits_le32(&imx_ccm->cbcmr,  in mxs_set_lcdclk()
731 			clrsetbits_le32(&imx_ccm->cscdr2,  in mxs_set_lcdclk()
739 			clrsetbits_le32(&imx_ccm->cscmr1,  in mxs_set_lcdclk()
753 		clrsetbits_le32(&imx_ccm->cscdr2,  in mxs_set_lcdclk()
761 		clrsetbits_le32(&imx_ccm->cscmr1,  in mxs_set_lcdclk()
804 		reg = readl(&imx_ccm->CCGR3);  in enable_lcdif_clock()
807 		writel(reg, &imx_ccm->CCGR3);  in enable_lcdif_clock()
810 			reg = readl(&imx_ccm->cscdr3);  in enable_lcdif_clock()
813 			writel(reg, &imx_ccm->cscdr3);  in enable_lcdif_clock()
815 			reg = readl(&imx_ccm->CCGR3);  in enable_lcdif_clock()
818 			writel(reg, &imx_ccm->CCGR3);  in enable_lcdif_clock()
827 	reg = readl(&imx_ccm->CCGR3);  in enable_lcdif_clock()
829 	writel(reg, &imx_ccm->CCGR3);  in enable_lcdif_clock()
831 	reg = readl(&imx_ccm->CCGR2);  in enable_lcdif_clock()
833 	writel(reg, &imx_ccm->CCGR2);  in enable_lcdif_clock()
837 		reg = readl(&imx_ccm->cscdr2);  in enable_lcdif_clock()
839 		writel(reg, &imx_ccm->cscdr2);  in enable_lcdif_clock()
842 		reg = readl(&imx_ccm->CCGR3);  in enable_lcdif_clock()
844 		writel(reg, &imx_ccm->CCGR3);  in enable_lcdif_clock()
846 		reg = readl(&imx_ccm->CCGR2);  in enable_lcdif_clock()
848 		writel(reg, &imx_ccm->CCGR2);  in enable_lcdif_clock()
864 		clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);  in enable_qspi_clk()
867 		reg = readl(&imx_ccm->cscmr1);  in enable_qspi_clk()
872 		writel(reg, &imx_ccm->cscmr1);  in enable_qspi_clk()
875 		setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);  in enable_qspi_clk()
883 		clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |  in enable_qspi_clk()
887 		reg = readl(&imx_ccm->cs2cdr);  in enable_qspi_clk()
893 		writel(reg, &imx_ccm->cs2cdr);  in enable_qspi_clk()
896 		setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |  in enable_qspi_clk()
954 	reg = readl(&imx_ccm->CCGR3);  in enable_fec_anatop_clock()
956 	writel(reg, &imx_ccm->CCGR3);  in enable_fec_anatop_clock()
962 	reg = readl(&imx_ccm->chsccdr);  in enable_fec_anatop_clock()
971 	writel(reg, &imx_ccm->chsccdr);  in enable_fec_anatop_clock()
974 	reg = readl(&imx_ccm->CCGR3);  in enable_fec_anatop_clock()
976 	writel(reg, &imx_ccm->CCGR3);  in enable_fec_anatop_clock()
985 	u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);  in get_usdhc_clk()
986 	u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);  in get_usdhc_clk()
1048 	struct mxc_ccm_reg *const imx_ccm  in enable_enet_pll()  local
1054 	reg = readl(&imx_ccm->analog_pll_enet);  in enable_enet_pll()
1056 	writel(reg, &imx_ccm->analog_pll_enet);  in enable_enet_pll()
1059 		if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)  in enable_enet_pll()
1065 	writel(reg, &imx_ccm->analog_pll_enet);  in enable_enet_pll()
1067 	writel(reg, &imx_ccm->analog_pll_enet);  in enable_enet_pll()
1075 	struct mxc_ccm_reg *const imx_ccm =  in ungate_sata_clock()  local
1079 	setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);  in ungate_sata_clock()
1090 	struct mxc_ccm_reg *const imx_ccm =  in disable_sata_clock()  local
1093 	clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);  in disable_sata_clock()
1100 	struct mxc_ccm_reg *const imx_ccm =  in ungate_pcie_clock()  local
1104 	setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);  in ungate_pcie_clock()
1163 		reg = __raw_readl(&imx_ccm->CCGR0);  in hab_caam_clock_enable()
1168 		__raw_writel(reg, &imx_ccm->CCGR0);  in hab_caam_clock_enable()
1171 		reg = __raw_readl(&imx_ccm->CCGR0);  in hab_caam_clock_enable()
1180 		__raw_writel(reg, &imx_ccm->CCGR0);  in hab_caam_clock_enable()
1184 	reg = __raw_readl(&imx_ccm->CCGR6);  in hab_caam_clock_enable()
1189 	__raw_writel(reg, &imx_ccm->CCGR6);  in hab_caam_clock_enable()
1471 	reg = __raw_readl(&imx_ccm->CCGR6);  in enable_eim_clk()
1476 	__raw_writel(reg, &imx_ccm->CCGR6);  in enable_eim_clk()