Lines Matching refs:CCGR3
105 addr = &imx_ccm->CCGR3; in enable_enet_clk()
804 reg = readl(&imx_ccm->CCGR3); in enable_lcdif_clock()
807 writel(reg, &imx_ccm->CCGR3); in enable_lcdif_clock()
815 reg = readl(&imx_ccm->CCGR3); in enable_lcdif_clock()
818 writel(reg, &imx_ccm->CCGR3); in enable_lcdif_clock()
827 reg = readl(&imx_ccm->CCGR3); in enable_lcdif_clock()
829 writel(reg, &imx_ccm->CCGR3); in enable_lcdif_clock()
842 reg = readl(&imx_ccm->CCGR3); in enable_lcdif_clock()
844 writel(reg, &imx_ccm->CCGR3); in enable_lcdif_clock()
864 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK); in enable_qspi_clk()
875 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK); in enable_qspi_clk()
954 reg = readl(&imx_ccm->CCGR3); in enable_fec_anatop_clock()
956 writel(reg, &imx_ccm->CCGR3); in enable_fec_anatop_clock()
974 reg = readl(&imx_ccm->CCGR3); in enable_fec_anatop_clock()
976 writel(reg, &imx_ccm->CCGR3); in enable_fec_anatop_clock()
1305 reg = readl(&mxc_ccm->CCGR3); in enable_ipu_clock()
1307 writel(reg, &mxc_ccm->CCGR3); in enable_ipu_clock()
1311 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK); in enable_ipu_clock()