Lines Matching refs:ldr

33 	ldr r0, =0xC0 |			/* tag RAM */ \
40 	ldr r3, [r4, #ROM_SI_REV]
63 	ldr r0, =AIPS1_BASE_ADDR
64 	ldr r1, =0x77777777
67 	ldr r0, =AIPS2_BASE_ADDR
83 	ldr r0, =M4IF_BASE_ADDR
85 	ldr r1, =0x00000203
90 	ldr r1, =0x00120125
93 	ldr r1, =0x001901A3
100 	ldr r0, =\pll
110 	ldr r1, =0x00001232
115 	ldr r1, [r2, #W_DP_OP]
119 	ldr r1, [r2, #W_DP_MFD]
123 	ldr r1, [r2, #W_DP_MFN]
127 	ldr r1, =0x00001232
129 1:	ldr r1, [r0, #PLL_DP_CTL]
137 	ldr r2, =\pll
139 	ldr r1, =0x00001236
141 1:	ldr r1, [r2, #PLL_DP_CTL]    /* Wait for lock */
145 	ldr r5, \freq
152 2:	ldr r1, [r2, #PLL_DP_CONFIG]
156 	ldr r1, =100		     /* Wait at least 4 us */
166 	ldr r0, =CCM_BASE_ADDR
169 	ldr r1, =0x3FFFFFFF
175 	ldr r1, =0x00030000
177 	ldr r1, =0x00FFF030
179 	ldr r1, =0x00000300
187 	ldr r1, =0x19239145
190 1:	ldr r1, [r0, #CLKCTL_CDHIPR]
208 	ldr r0, =CCM_BASE_ADDR
209 	ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
211 	ldr r1, =0x13239145
216 	ldr r0, =CCM_BASE_ADDR
217 	ldr r1, =0x19239145
219 	ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
225 	ldr r0, =ARM_BASE_ADDR
226 	ldr r1, =0x00000725
229 	ldr r0, =CCM_BASE_ADDR
232 	ldr r3, [r4, #ROM_SI_REV]
244 	ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
247 	ldr r1, =CONFIG_SYS_CLKTL_CBCDR
251 	ldr r1, =0xFFFFFFFF
261 	ldr r1, =0xA5A2A020
263 	ldr r1, =0x00C30321
266 1:	ldr r1, [r0, #CLKCTL_CDHIPR]
277 	ldr r0, =CCM_BASE_ADDR
280 	ldr r1, =0x3FFFFFFF
286 	ldr r1, =0x00030000
288 	ldr r1, =0x00FFF030
290 	ldr r1, =0x0F00030F
302 	ldr r0, =CCM_BASE_ADDR
303 	ldr r1, =0x00015154
305 	ldr r1, =0x02898945
308 1:      ldr r1, [r0, #CLKCTL_CDHIPR]
315 	ldr r0, =CCM_BASE_ADDR
316 	ldr r1, =0x00888945
319 	ldr r1, =0x00016154
323 	ldr r1, [r0, #CLKCTL_CSCMR1]
329 1:      ldr r1, [r0, #CLKCTL_CDHIPR]
338 	ldr r0, =ARM_BASE_ADDR
339 	ldr r1, =0x00000124
342 	ldr r0, =CCM_BASE_ADDR
351 	ldr r1, [r0, #CLKCTL_CSCDR1]
357 	ldr r1, =0xFFFFFFFF
383 	ldr r0, =GPIO1_BASE_ADDR
384 	ldr r1, [r0, #0x0]
387 	ldr r1, [r0, #0x4]