Lines Matching refs:str

65 	str r1, [r0, #0x0]
66 	str r1, [r0, #0x4]
68 	str r1, [r0, #0x0]
69 	str r1, [r0, #0x4]
86 	str r1, [r0, #0x40]
88 	str r4, [r0, #0x44]
91 	str r1, [r0, #0x9C]
94 	str r1, [r0, #0x48]
111 	str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
113 	str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
116 	str r1, [r0, #PLL_DP_OP]
117 	str r1, [r0, #PLL_DP_HFS_OP]
120 	str r1, [r0, #PLL_DP_MFD]
121 	str r1, [r0, #PLL_DP_HFS_MFD]
124 	str r1, [r0, #PLL_DP_MFN]
125 	str r1, [r0, #PLL_DP_HFS_MFN]
128 	str r1, [r0, #PLL_DP_CTL]
138 	str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
140 	str r1, [r2, #PLL_DP_CTL]    /* Restart PLL with PLM=1 */
146 	str r5, [r2, #PLL_DP_MFN]    /* Modify MFN value */
147 	str r5, [r2, #PLL_DP_HFS_MFN]
150 	str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
161 	str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
170 	str r1, [r0, #CLKCTL_CCGR0]
171 	str r4, [r0, #CLKCTL_CCGR1]
172 	str r4, [r0, #CLKCTL_CCGR2]
173 	str r4, [r0, #CLKCTL_CCGR3]
176 	str r1, [r0, #CLKCTL_CCGR4]
178 	str r1, [r0, #CLKCTL_CCGR5]
180 	str r1, [r0, #CLKCTL_CCGR6]
184 	str r1, [r0, #CLKCTL_CCDR]
188 	str r1, [r0, #CLKCTL_CBCDR]
196 	str r1, [r0, #CLKCTL_CCSR]
210 	str r1, [r0, #CLKCTL_CBCMR]
212 	str r1, [r0, #CLKCTL_CBCDR]
218 	str r1, [r0, #CLKCTL_CBCDR]
220 	str r1, [r0, #CLKCTL_CBCMR]
227 	str r1, [r0, #0x14]
237 	str r1, [r0, #CLKCTL_CACRR]
240 	str r4, [r0, #CLKCTL_CCSR]
245 	str r1, [r0, #CLKCTL_CBCMR]
248 	str r1, [r0, #CLKCTL_CBCDR]
252 	str r1, [r0, #CLKCTL_CCGR0]
253 	str r1, [r0, #CLKCTL_CCGR1]
254 	str r1, [r0, #CLKCTL_CCGR2]
255 	str r1, [r0, #CLKCTL_CCGR3]
256 	str r1, [r0, #CLKCTL_CCGR4]
257 	str r1, [r0, #CLKCTL_CCGR5]
258 	str r1, [r0, #CLKCTL_CCGR6]
262 	str r1, [r0, #CLKCTL_CSCMR1]
264 	str r1, [r0, #CLKCTL_CSCDR1]
270 	str r4, [r0, #CLKCTL_CCDR]
275 	str r1, [r0, #CLKCTL_CCOSR]
281 	str r1, [r0, #CLKCTL_CCGR0]
282 	str r4, [r0, #CLKCTL_CCGR1]
283 	str r4, [r0, #CLKCTL_CCGR2]
284 	str r4, [r0, #CLKCTL_CCGR3]
285 	str r4, [r0, #CLKCTL_CCGR7]
287 	str r1, [r0, #CLKCTL_CCGR4]
289 	str r1, [r0, #CLKCTL_CCGR5]
291 	str r1, [r0, #CLKCTL_CCGR6]
295 	str r1, [r0, #CLKCTL_CCSR]
304 	str r1, [r0, #CLKCTL_CBCMR]
306 	str r1, [r0, #CLKCTL_CBCDR]
317 	str r1, [r0, #CLKCTL_CBCDR]
320 	str r1, [r0, #CLKCTL_CBCMR]
326 	str r1, [r0, #CLKCTL_CSCMR1]
340 	str r1, [r0, #0x14]
344 	str r1, [r0, #CLKCTL_CACRR]
348 	str r1, [r0, #CLKCTL_CCSR]
354 	str r1, [r0, #CLKCTL_CSCDR1]
358 	str r1, [r0, #CLKCTL_CCGR0]
359 	str r1, [r0, #CLKCTL_CCGR1]
360 	str r1, [r0, #CLKCTL_CCGR2]
361 	str r1, [r0, #CLKCTL_CCGR3]
362 	str r1, [r0, #CLKCTL_CCGR4]
363 	str r1, [r0, #CLKCTL_CCGR5]
364 	str r1, [r0, #CLKCTL_CCGR6]
365 	str r1, [r0, #CLKCTL_CCGR7]
368 	str r1, [r0, #CLKCTL_CCDR]
373 	str r1, [r0, #CLKCTL_CCOSR]
386 	str r1, [r0, #0x0]
389 	str r1, [r0, #0x4]