Lines Matching full:r1
18 mrc 15, 0, r1, c1, c0, 1
19 orr r1, r1, #(1 << 5) /* enable L1NEON bit */
20 mcr 15, 0, r1, c1, c0, 1
64 ldr r1, =0x77777777
65 str r1, [r0, #0x0]
66 str r1, [r0, #0x4]
68 str r1, [r0, #0x0]
69 str r1, [r0, #0x4]
85 ldr r1, =0x00000203
86 str r1, [r0, #0x40]
90 ldr r1, =0x00120125
91 str r1, [r0, #0x9C]
93 ldr r1, =0x001901A3
94 str r1, [r0, #0x48]
110 ldr r1, =0x00001232
111 str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
112 mov r1, #0x2
113 str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
115 ldr r1, [r2, #W_DP_OP]
116 str r1, [r0, #PLL_DP_OP]
117 str r1, [r0, #PLL_DP_HFS_OP]
119 ldr r1, [r2, #W_DP_MFD]
120 str r1, [r0, #PLL_DP_MFD]
121 str r1, [r0, #PLL_DP_HFS_MFD]
123 ldr r1, [r2, #W_DP_MFN]
124 str r1, [r0, #PLL_DP_MFN]
125 str r1, [r0, #PLL_DP_HFS_MFN]
127 ldr r1, =0x00001232
128 str r1, [r0, #PLL_DP_CTL]
129 1: ldr r1, [r0, #PLL_DP_CTL]
130 ands r1, r1, #0x1
139 ldr r1, =0x00001236
140 str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
141 1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
142 ands r1, r1, #0x1
149 mov r1, #0x1
150 str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
152 2: ldr r1, [r2, #PLL_DP_CONFIG]
153 tst r1, #1
156 ldr r1, =100 /* Wait at least 4 us */
157 3: subs r1, r1, #1
160 mov r1, #0x2
161 str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
169 ldr r1, =0x3FFFFFFF
170 str r1, [r0, #CLKCTL_CCGR0]
175 ldr r1, =0x00030000
176 str r1, [r0, #CLKCTL_CCGR4]
177 ldr r1, =0x00FFF030
178 str r1, [r0, #CLKCTL_CCGR5]
179 ldr r1, =0x00000300
180 str r1, [r0, #CLKCTL_CCGR6]
183 mov r1, #0x60000
184 str r1, [r0, #CLKCTL_CCDR]
187 ldr r1, =0x19239145
188 str r1, [r0, #CLKCTL_CBCDR]
190 1: ldr r1, [r0, #CLKCTL_CDHIPR]
191 cmp r1, #0x0
195 mov r1, #0x4
196 str r1, [r0, #CLKCTL_CCSR]
209 ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
210 str r1, [r0, #CLKCTL_CBCMR]
211 ldr r1, =0x13239145
212 str r1, [r0, #CLKCTL_CBCDR]
217 ldr r1, =0x19239145
218 str r1, [r0, #CLKCTL_CBCDR]
219 ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
220 str r1, [r0, #CLKCTL_CBCMR]
226 ldr r1, =0x00000725
227 str r1, [r0, #0x14]
234 movls r1, #0x1
235 movhi r1, #0
237 str r1, [r0, #CLKCTL_CACRR]
244 ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
245 str r1, [r0, #CLKCTL_CBCMR]
247 ldr r1, =CONFIG_SYS_CLKTL_CBCDR
248 str r1, [r0, #CLKCTL_CBCDR]
251 ldr r1, =0xFFFFFFFF
252 str r1, [r0, #CLKCTL_CCGR0]
253 str r1, [r0, #CLKCTL_CCGR1]
254 str r1, [r0, #CLKCTL_CCGR2]
255 str r1, [r0, #CLKCTL_CCGR3]
256 str r1, [r0, #CLKCTL_CCGR4]
257 str r1, [r0, #CLKCTL_CCGR5]
258 str r1, [r0, #CLKCTL_CCGR6]
261 ldr r1, =0xA5A2A020
262 str r1, [r0, #CLKCTL_CSCMR1]
263 ldr r1, =0x00C30321
264 str r1, [r0, #CLKCTL_CSCDR1]
266 1: ldr r1, [r0, #CLKCTL_CDHIPR]
267 cmp r1, #0x0
273 mov r1, #0x000A0000
274 add r1, r1, #0x00000F0
275 str r1, [r0, #CLKCTL_CCOSR]
280 ldr r1, =0x3FFFFFFF
281 str r1, [r0, #CLKCTL_CCGR0]
286 ldr r1, =0x00030000
287 str r1, [r0, #CLKCTL_CCGR4]
288 ldr r1, =0x00FFF030
289 str r1, [r0, #CLKCTL_CCGR5]
290 ldr r1, =0x0F00030F
291 str r1, [r0, #CLKCTL_CCGR6]
294 mov r1, #0x4
295 str r1, [r0, #CLKCTL_CCSR]
303 ldr r1, =0x00015154
304 str r1, [r0, #CLKCTL_CBCMR]
305 ldr r1, =0x02898945
306 str r1, [r0, #CLKCTL_CBCDR]
308 1: ldr r1, [r0, #CLKCTL_CDHIPR]
309 cmp r1, #0x0
316 ldr r1, =0x00888945
317 str r1, [r0, #CLKCTL_CBCDR]
319 ldr r1, =0x00016154
320 str r1, [r0, #CLKCTL_CBCMR]
323 ldr r1, [r0, #CLKCTL_CSCMR1]
324 and r1, r1, #0xfcffffff
325 orr r1, r1, #0x01000000
326 str r1, [r0, #CLKCTL_CSCMR1]
329 1: ldr r1, [r0, #CLKCTL_CDHIPR]
330 cmp r1, #0x0
339 ldr r1, =0x00000124
340 str r1, [r0, #0x14]
343 mov r1, #0
344 str r1, [r0, #CLKCTL_CACRR]
347 mov r1, #0x0
348 str r1, [r0, #CLKCTL_CCSR]
351 ldr r1, [r0, #CLKCTL_CSCDR1]
352 and r1, r1, #0xffffffc0
353 orr r1, r1, #0x0a
354 str r1, [r0, #CLKCTL_CSCDR1]
357 ldr r1, =0xFFFFFFFF
358 str r1, [r0, #CLKCTL_CCGR0]
359 str r1, [r0, #CLKCTL_CCGR1]
360 str r1, [r0, #CLKCTL_CCGR2]
361 str r1, [r0, #CLKCTL_CCGR3]
362 str r1, [r0, #CLKCTL_CCGR4]
363 str r1, [r0, #CLKCTL_CCGR5]
364 str r1, [r0, #CLKCTL_CCGR6]
365 str r1, [r0, #CLKCTL_CCGR7]
367 mov r1, #0x00000
368 str r1, [r0, #CLKCTL_CCDR]
371 mov r1, #0x000A0000
372 add r1, r1, #0x00000F0
373 str r1, [r0, #CLKCTL_CCOSR]
384 ldr r1, [r0, #0x0]
385 orr r1, r1, #1 << 23
386 str r1, [r0, #0x0]
387 ldr r1, [r0, #0x4]
388 orr r1, r1, #1 << 23
389 str r1, [r0, #0x4]