Lines Matching full:r0
28 mrc 15, 0, r0, c1, c0, 1
29 bic r0, r0, #0x2
30 mcr 15, 0, r0, c1, c0, 1
33 ldr r0, =0xC0 | /* tag RAM */ \
44 orrls r0, r0, #1 << 25
47 mcr 15, 1, r0, c9, c0, 2
50 mrc 15, 0, r0, c1, c0, 1
51 orr r0, r0, #2
52 mcr 15, 0, r0, c1, c0, 1
63 ldr r0, =AIPS1_BASE_ADDR
65 str r1, [r0, #0x0]
66 str r1, [r0, #0x4]
67 ldr r0, =AIPS2_BASE_ADDR
68 str r1, [r0, #0x0]
69 str r1, [r0, #0x4]
83 ldr r0, =M4IF_BASE_ADDR
86 str r1, [r0, #0x40]
88 str r4, [r0, #0x44]
91 str r1, [r0, #0x9C]
94 str r1, [r0, #0x48]
100 ldr r0, =\pll
111 str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
113 str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
116 str r1, [r0, #PLL_DP_OP]
117 str r1, [r0, #PLL_DP_HFS_OP]
120 str r1, [r0, #PLL_DP_MFD]
121 str r1, [r0, #PLL_DP_HFS_MFD]
124 str r1, [r0, #PLL_DP_MFN]
125 str r1, [r0, #PLL_DP_HFS_MFN]
128 str r1, [r0, #PLL_DP_CTL]
129 1: ldr r1, [r0, #PLL_DP_CTL]
166 ldr r0, =CCM_BASE_ADDR
170 str r1, [r0, #CLKCTL_CCGR0]
171 str r4, [r0, #CLKCTL_CCGR1]
172 str r4, [r0, #CLKCTL_CCGR2]
173 str r4, [r0, #CLKCTL_CCGR3]
176 str r1, [r0, #CLKCTL_CCGR4]
178 str r1, [r0, #CLKCTL_CCGR5]
180 str r1, [r0, #CLKCTL_CCGR6]
184 str r1, [r0, #CLKCTL_CCDR]
188 str r1, [r0, #CLKCTL_CBCDR]
190 1: ldr r1, [r0, #CLKCTL_CDHIPR]
196 str r1, [r0, #CLKCTL_CCSR]
208 ldr r0, =CCM_BASE_ADDR
210 str r1, [r0, #CLKCTL_CBCMR]
212 str r1, [r0, #CLKCTL_CBCDR]
216 ldr r0, =CCM_BASE_ADDR
218 str r1, [r0, #CLKCTL_CBCDR]
220 str r1, [r0, #CLKCTL_CBCMR]
225 ldr r0, =ARM_BASE_ADDR
227 str r1, [r0, #0x14]
229 ldr r0, =CCM_BASE_ADDR
237 str r1, [r0, #CLKCTL_CACRR]
240 str r4, [r0, #CLKCTL_CCSR]
245 str r1, [r0, #CLKCTL_CBCMR]
248 str r1, [r0, #CLKCTL_CBCDR]
252 str r1, [r0, #CLKCTL_CCGR0]
253 str r1, [r0, #CLKCTL_CCGR1]
254 str r1, [r0, #CLKCTL_CCGR2]
255 str r1, [r0, #CLKCTL_CCGR3]
256 str r1, [r0, #CLKCTL_CCGR4]
257 str r1, [r0, #CLKCTL_CCGR5]
258 str r1, [r0, #CLKCTL_CCGR6]
262 str r1, [r0, #CLKCTL_CSCMR1]
264 str r1, [r0, #CLKCTL_CSCDR1]
266 1: ldr r1, [r0, #CLKCTL_CDHIPR]
270 str r4, [r0, #CLKCTL_CCDR]
275 str r1, [r0, #CLKCTL_CCOSR]
277 ldr r0, =CCM_BASE_ADDR
281 str r1, [r0, #CLKCTL_CCGR0]
282 str r4, [r0, #CLKCTL_CCGR1]
283 str r4, [r0, #CLKCTL_CCGR2]
284 str r4, [r0, #CLKCTL_CCGR3]
285 str r4, [r0, #CLKCTL_CCGR7]
287 str r1, [r0, #CLKCTL_CCGR4]
289 str r1, [r0, #CLKCTL_CCGR5]
291 str r1, [r0, #CLKCTL_CCGR6]
295 str r1, [r0, #CLKCTL_CCSR]
302 ldr r0, =CCM_BASE_ADDR
304 str r1, [r0, #CLKCTL_CBCMR]
306 str r1, [r0, #CLKCTL_CBCDR]
308 1: ldr r1, [r0, #CLKCTL_CDHIPR]
315 ldr r0, =CCM_BASE_ADDR
317 str r1, [r0, #CLKCTL_CBCDR]
320 str r1, [r0, #CLKCTL_CBCMR]
323 ldr r1, [r0, #CLKCTL_CSCMR1]
326 str r1, [r0, #CLKCTL_CSCMR1]
329 1: ldr r1, [r0, #CLKCTL_CDHIPR]
338 ldr r0, =ARM_BASE_ADDR
340 str r1, [r0, #0x14]
342 ldr r0, =CCM_BASE_ADDR
344 str r1, [r0, #CLKCTL_CACRR]
348 str r1, [r0, #CLKCTL_CCSR]
351 ldr r1, [r0, #CLKCTL_CSCDR1]
354 str r1, [r0, #CLKCTL_CSCDR1]
358 str r1, [r0, #CLKCTL_CCGR0]
359 str r1, [r0, #CLKCTL_CCGR1]
360 str r1, [r0, #CLKCTL_CCGR2]
361 str r1, [r0, #CLKCTL_CCGR3]
362 str r1, [r0, #CLKCTL_CCGR4]
363 str r1, [r0, #CLKCTL_CCGR5]
364 str r1, [r0, #CLKCTL_CCGR6]
365 str r1, [r0, #CLKCTL_CCGR7]
368 str r1, [r0, #CLKCTL_CCDR]
373 str r1, [r0, #CLKCTL_CCOSR]
383 ldr r0, =GPIO1_BASE_ADDR
384 ldr r1, [r0, #0x0]
386 str r1, [r0, #0x0]
387 ldr r1, [r0, #0x4]
389 str r1, [r0, #0x4]