74 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;  variable
78 	clrsetbits_le32(&mxc_ccm->cscmr1,  in set_usboh3_clk()
81 	clrsetbits_le32(&mxc_ccm->cscdr1,  in set_usboh3_clk()
92 	clrsetbits_le32(&mxc_ccm->CCGR2,  in enable_usboh3_clk()
112 		setbits_le32(&mxc_ccm->CCGR1, mask);  in enable_i2c_clk()
114 		clrbits_le32(&mxc_ccm->CCGR1, mask);  in enable_i2c_clk()
121 	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);  in set_usb_phy_clk()
129 	clrsetbits_le32(&mxc_ccm->CCGR2,  in enable_usb_phy1_clk()
143 	clrsetbits_le32(&mxc_ccm->CCGR4,  in enable_usb_phy1_clk()
152 	clrsetbits_le32(&mxc_ccm->CCGR4,  in enable_usb_phy2_clk()
219 	u32 ccr = readl(&mxc_ccm->ccr);  in get_fpm()
236 	u32 ccsr = readl(&mxc_ccm->ccsr);  in get_lp_apm()
257 	reg = MXC_CCM_CACRR_ARM_PODF_RD(readl(&mxc_ccm->cacrr));  in get_mcu_main_clk()
269 	reg = readl(&mxc_ccm->cbcdr);  in get_periph_clk()
272 	reg = readl(&mxc_ccm->cbcmr);  in get_periph_clk()
295 	reg = readl(&mxc_ccm->cbcdr);  in get_ipg_clk()
308 	if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)  in get_ipg_per_clk()
311 	if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL)  in get_ipg_per_clk()
315 	podf = readl(&mxc_ccm->cbcdr);  in get_ipg_per_clk()
352 	reg = readl(&mxc_ccm->cscmr1);  in get_uart_clk()
356 	reg = readl(&mxc_ccm->cscdr1);  in get_uart_clk()
370 	u32 cscmr1 = readl(&mxc_ccm->cscmr1);  in imx_get_cspiclk()
371 	u32 cscdr2 = readl(&mxc_ccm->cscdr2);  in imx_get_cspiclk()
387 	u32 cscmr1 = readl(&mxc_ccm->cscmr1);  in get_esdhc_clk()
388 	u32 cscdr1 = readl(&mxc_ccm->cscdr1);  in get_esdhc_clk()
421 	u32 cbcdr = readl(&mxc_ccm->cbcdr);  in get_axi_a_clk()
429 	u32 cbcdr = readl(&mxc_ccm->cbcdr);  in get_axi_b_clk()
437 	u32 cbcdr = readl(&mxc_ccm->cbcdr);  in get_emi_slow_clk()
450 	u32 cbcmr = readl(&mxc_ccm->cbcmr);  in get_ddr_clk()
453 	u32 cbcdr = readl(&mxc_ccm->cbcdr);  in get_ddr_clk()
648 	u32 ccsr = readl(&mxc_ccm->ccsr);  in config_pll_clk()
655 				&mxc_ccm->ccsr);  in config_pll_clk()
661 				&mxc_ccm->ccsr);  in config_pll_clk()
666 				&mxc_ccm->ccsr);  in config_pll_clk()
672 				&mxc_ccm->ccsr);  in config_pll_clk()
677 				&mxc_ccm->ccsr);  in config_pll_clk()
683 				&mxc_ccm->ccsr);  in config_pll_clk()
689 				&mxc_ccm->ccsr);  in config_pll_clk()
695 				&mxc_ccm->ccsr);  in config_pll_clk()
735 	clrsetbits_le32(&mxc_ccm->cbcdr,  in config_nfc_clk()
738 	while (readl(&mxc_ccm->cdhipr) != 0)  in config_nfc_clk()
747 	clrsetbits_le32(&mxc_ccm->CCGR5,  in enable_nfc_clk()
756 		setbits_le32(&mxc_ccm->cgpr,  in enable_efuse_prog_supply()
759 		clrbits_le32(&mxc_ccm->cgpr,  in enable_efuse_prog_supply()
772 	if (readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {  in config_periph_clk()
780 				readl(&mxc_ccm->cbcmr))) {  in config_periph_clk()
799 	u32 cbcmr = readl(&mxc_ccm->cbcmr);  in config_ddr_clk()
834 	clrsetbits_le32(&mxc_ccm->cbcdr, 0x7 << shift, (div - 1) << shift);  in config_ddr_clk()
835 	while (readl(&mxc_ccm->cdhipr) != 0)  in config_ddr_clk()
837 	writel(0x0, &mxc_ccm->ccdr);  in config_ddr_clk()