161 static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)  in decode_pll()  function
242 		ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);  in get_lp_apm()
258 	freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);  in get_mcu_main_clk()
271 		return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);  in get_periph_clk()
275 		return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);  in get_periph_clk()
277 		return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);  in get_periph_clk()
329 		freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);  in get_standard_pll_sel_clk()
332 		freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);  in get_standard_pll_sel_clk()
335 		freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);  in get_standard_pll_sel_clk()
457 		ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);  in get_ddr_clk()
921 	freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);  in do_mx5_showclocks()
923 	freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);  in do_mx5_showclocks()
925 	freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);  in do_mx5_showclocks()
928 	freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);  in do_mx5_showclocks()