323 static u32 get_standard_pll_sel_clk(u32 clk_sel)  in get_standard_pll_sel_clk()  argument
327 	switch (clk_sel & 0x3) {  in get_standard_pll_sel_clk()
350 	unsigned int clk_sel, freq, reg, pred, podf;  in get_uart_clk()  local
353 	clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg);  in get_uart_clk()
354 	freq = get_standard_pll_sel_clk(clk_sel);  in get_uart_clk()
369 	u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq;  in imx_get_cspiclk()  local
375 	clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1);  in imx_get_cspiclk()
376 	freq = get_standard_pll_sel_clk(clk_sel);  in imx_get_cspiclk()
386 	u32 clk_sel = 0, pred = 0, podf = 0, freq = 0;  in get_esdhc_clk()  local
392 		clk_sel = MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(cscmr1);  in get_esdhc_clk()
397 		clk_sel = MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(cscmr1);  in get_esdhc_clk()
415 	freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1));  in get_esdhc_clk()
798 	s32 shift = 0, clk_sel, div = 1;  in config_ddr_clk()  local
809 	clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);  in config_ddr_clk()
810 	switch (clk_sel) {  in config_ddr_clk()