255 	u32 reg, freq;  in get_mcu_main_clk()  local
258 	freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);  in get_mcu_main_clk()
259 	return freq / (reg + 1);  in get_mcu_main_clk()
291 	uint32_t freq, reg, div;  in get_ipg_clk()  local
293 	freq = get_ahb_clk();  in get_ipg_clk()
298 	return freq / div;  in get_ipg_clk()
306 	u32 freq, pred1, pred2, podf;  in get_ipg_per_clk()  local
312 		freq = get_lp_apm();  in get_ipg_per_clk()
314 		freq = get_periph_clk();  in get_ipg_per_clk()
319 	return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1));  in get_ipg_per_clk()
325 	u32 freq = 0;  in get_standard_pll_sel_clk()  local
329 		freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);  in get_standard_pll_sel_clk()
332 		freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);  in get_standard_pll_sel_clk()
335 		freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);  in get_standard_pll_sel_clk()
338 		freq = get_lp_apm();  in get_standard_pll_sel_clk()
342 	return freq;  in get_standard_pll_sel_clk()
350 	unsigned int clk_sel, freq, reg, pred, podf;  in get_uart_clk()  local
354 	freq = get_standard_pll_sel_clk(clk_sel);  in get_uart_clk()
359 	freq /= (pred + 1) * (podf + 1);  in get_uart_clk()
361 	return freq;  in get_uart_clk()
369 	u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq;  in imx_get_cspiclk()  local
376 	freq = get_standard_pll_sel_clk(clk_sel);  in imx_get_cspiclk()
377 	ret_val = freq / ((pre_pdf + 1) * (pdf + 1));  in imx_get_cspiclk()
386 	u32 clk_sel = 0, pred = 0, podf = 0, freq = 0;  in get_esdhc_clk()  local
415 	freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1));  in get_esdhc_clk()
416 	return freq;  in get_esdhc_clk()
559 	 * Make sure targeted freq is in the valid range.  in calc_pll_params()
706 static int config_core_clk(u32 ref, u32 freq)  in config_core_clk()  argument
714 	ret = calc_pll_params(ref, freq, &pll_param);  in config_core_clk()
765 static int config_periph_clk(u32 ref, u32 freq)  in config_periph_clk()  argument
773 		ret = calc_pll_params(ref, freq, &pll_param);  in config_periph_clk()
845  * it is. So it assumes the PLL output freq is the same as the expected
862 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)  in mxc_set_clock()  argument
864 	freq *= SZ_DEC_1M;  in mxc_set_clock()
868 		if (config_core_clk(ref, freq))  in mxc_set_clock()
872 		if (config_periph_clk(ref, freq))  in mxc_set_clock()
876 		if (config_ddr_clk(freq))  in mxc_set_clock()
880 		if (config_nfc_clk(freq))  in mxc_set_clock()
919 	u32 freq;  in do_mx5_showclocks()  local
921 	freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);  in do_mx5_showclocks()
922 	printf("PLL1       %8d MHz\n", freq / 1000000);  in do_mx5_showclocks()
923 	freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);  in do_mx5_showclocks()
924 	printf("PLL2       %8d MHz\n", freq / 1000000);  in do_mx5_showclocks()
925 	freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);  in do_mx5_showclocks()
926 	printf("PLL3       %8d MHz\n", freq / 1000000);  in do_mx5_showclocks()
928 	freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);  in do_mx5_showclocks()
929 	printf("PLL4       %8d MHz\n", freq / 1000000);  in do_mx5_showclocks()