arm/mach-imx/cache.c

4  * SPDX-License-Identifier:     GPL-2.0+
11 #include <asm/mach-imx/sys_proto.h>
24 	/* Enable D-cache. I-cache is already enabled in start.S */  in enable_caches()
48 	 * Must disable the L2 before changing the latency parameters  in v7_outer_cache_enable()
51 	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);  in v7_outer_cache_enable()
55 	 * is cleared, PL310 treats Normal Shared Non-cacheable  in v7_outer_cache_enable()
56 	 * accesses as Cacheable no-allocate.  in v7_outer_cache_enable()
58 	setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);  in v7_outer_cache_enable()
61 		val = readl(&iomux->gpr[11]);  in v7_outer_cache_enable()
63 			/* L2 cache configured as OCRAM, reset it */  in v7_outer_cache_enable()
65 			writel(val, &iomux->gpr[11]);  in v7_outer_cache_enable()
69 	writel(0x132, &pl310->pl310_tag_latency_ctrl);  in v7_outer_cache_enable()
70 	writel(0x132, &pl310->pl310_data_latency_ctrl);  in v7_outer_cache_enable()
72 	val = readl(&pl310->pl310_prefetch_ctrl);  in v7_outer_cache_enable()
74 	/* Turn on the L2 I/D prefetch */  in v7_outer_cache_enable()
78 	 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0  in v7_outer_cache_enable()
79 	 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2  in v7_outer_cache_enable()
81 	 * ID: 752271: Double linefill feature can cause data corruption  in v7_outer_cache_enable()
82 	 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2  in v7_outer_cache_enable()
90 	writel(val, &pl310->pl310_prefetch_ctrl);  in v7_outer_cache_enable()
92 	val = readl(&pl310->pl310_power_ctrl);  in v7_outer_cache_enable()
95 	writel(val, &pl310->pl310_power_ctrl);  in v7_outer_cache_enable()
97 	setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);  in v7_outer_cache_enable()
104 	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);  in v7_outer_cache_disable()