Lines Matching +full:0 +full:x02020000

15 	ldr     r2, =0x02073000		@ r2: target address
29  * This workaround code is relocated to the address 0x02073000
31  * (Base Address - 0x02020000, Limit Address - 0x020740000).
44  * Resume address - 0x2073008
45  * Resume flag - 0x207300C
48  * Switch address - 0x2073018
51  * Hotplug address - 0x207301C
54  * C2 address - 0x2073024
57  * CPU0 state - 0x2073028
58  * CPU1 state - 0x207302C
59  * CPU2 state - 0x2073030
60  * CPU3 state - 0x2073034
63  * CPU0 gic state - 0x2073038
64  * CPU1 gic state - 0x207303C
65  * CPU2 gic state - 0x2073040
66  * CPU3 gic state - 0x2073044
77 	.word   0x0		     @ REG0: RESUME_ADDR
78 	.word   0x0		     @ REG1: RESUME_FLAG
79 	.word   0x0		     @ REG2
80 	.word   0x0		     @ REG3
82 	.word   0x0		     @ REG4: SWITCH_ADDR
84 	.word   0x0		     @ REG5: CPU1_BOOT_REG
85 	.word   0x0		     @ REG6
87 	.word   0x0		     @ REG7: REG_C2_ADDR
89 	.word   0x1		     @ CPU0_STATE : RESET
90 	.word   0x2		     @ CPU1_STATE : SECONDARY RESET
91 	.word   0x2		     @ CPU2_STATE : SECONDARY RESET
92 	.word   0x2		     @ CPU3_STATE : SECONDARY RESET
94 	.word   0x0		     @ CPU0 - GICD_IGROUPR0
95 	.word   0x0		     @ CPU1 - GICD_IGROUPR0
96 	.word   0x0		     @ CPU2 - GICD_IGROUPR0
97 	.word   0x0		     @ CPU3 - GICD_IGROUPR0
100 	mrc     p15, 0, r7, c0, c0, 5   @ read MPIDR
101 	and     r7, r7, #0xf	    @ r7 = cpu id
109 	ldr     r0, =(0x10040000 + 0x804)
111 	cmp     r1, #0x0
112 	movne   r1, #0x0
115 	ldrne   r1, =(0x10040000 + 0x800)
117 	tst     r10, #(1 << 0)
118 	ldrne   pc, =0x23e00000
122 	cmp     r1, #0x0