Lines Matching +full:0 +full:x00010002
29 #define ASYNC_CONFIG 0x10010350
32 #define MUX_HPM_SEL_MOUTAPLL 0x0
33 #define MUX_HPM_SEL_SCLKMPLL 0x1
34 #define MUX_CORE_SEL_MOUTAPLL 0x0
35 #define MUX_CORE_SEL_SCLKMPLL 0x1
36 #define MUX_MPLL_SEL_FILPLL 0x0
37 #define MUX_MPLL_SEL_MOUTMPLLFOUT 0x1
38 #define MUX_APLL_SEL_FILPLL 0x0
39 #define MUX_APLL_SEL_MOUTMPLLFOUT 0x1
43 | (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
46 #define APLL_RATIO 0x0
47 #define PCLK_DBG_RATIO 0x1
48 #define ATB_RATIO 0x3
49 #define PERIPH_RATIO 0x3
50 #define COREM1_RATIO 0x7
51 #define COREM0_RATIO 0x3
52 #define CORE_RATIO 0x0
59 | (CORE_RATIO << 0))
62 #define HPM_RATIO 0x0
63 #define COPY_RATIO 0x3
67 #define MUX_PWI_SEL_XXTI 0x0
68 #define MUX_PWI_SEL_XUSBXTI 0x1
69 #define MUX_PWI_SEL_SCLK_HDMI24M 0x2
70 #define MUX_PWI_SEL_SCLK_USBPHY0 0x3
71 #define MUX_PWI_SEL_SCLK_USBPHY1 0x4
72 #define MUX_PWI_SEL_SCLK_HDMIPHY 0x5
73 #define MUX_PWI_SEL_SCLKMPLL 0x6
74 #define MUX_PWI_SEL_SCLKEPLL 0x7
75 #define MUX_PWI_SEL_SCLKVPLL 0x8
76 #define MUX_DPHY_SEL_SCLKMPLL 0x0
77 #define MUX_DPHY_SEL_SCLKAPLL 0x1
78 #define MUX_DMC_BUS_SEL_SCLKMPLL 0x0
79 #define MUX_DMC_BUS_SEL_SCLKAPLL 0x1
85 #define CORE_TIMERS_RATIO 0x1
86 #define COPY2_RATIO 0x3
87 #define DMCP_RATIO 0x1
88 #define DMCD_RATIO 0x1
89 #define DMC_RATIO 0x1
90 #define DPHY_RATIO 0x1
91 #define ACP_PCLK_RATIO 0x1
92 #define ACP_RATIO 0x3
100 | (ACP_RATIO << 0))
103 #define DPM_RATIO 0x1
104 #define DVSEM_RATIO 0x1
105 #define PWI_RATIO 0x1
111 #define MUX_ONENAND_SEL_ACLK_133 0x0
112 #define MUX_ONENAND_SEL_ACLK_160 0x1
113 #define MUX_ACLK_133_SEL_SCLKMPLL 0x0
114 #define MUX_ACLK_133_SEL_SCLKAPLL 0x1
115 #define MUX_ACLK_160_SEL_SCLKMPLL 0x0
116 #define MUX_ACLK_160_SEL_SCLKAPLL 0x1
117 #define MUX_ACLK_100_SEL_SCLKMPLL 0x0
118 #define MUX_ACLK_100_SEL_SCLKAPLL 0x1
119 #define MUX_ACLK_200_SEL_SCLKMPLL 0x0
120 #define MUX_ACLK_200_SEL_SCLKAPLL 0x1
121 #define MUX_VPLL_SEL_FINPLL 0x0
122 #define MUX_VPLL_SEL_FOUTVPLL 0x1
123 #define MUX_EPLL_SEL_FINPLL 0x0
124 #define MUX_EPLL_SEL_FOUTEPLL 0x1
125 #define MUX_ONENAND_1_SEL_MOUTONENAND 0x0
126 #define MUX_ONENAND_1_SEL_SCLKVPLL 0x1
134 | (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
137 #define VPLLSRC_SEL_FINPLL 0x0
138 #define VPLLSRC_SEL_SCLKHDMI24M 0x1
142 #define ONENAND_RATIO 0x0
143 #define ACLK_133_RATIO 0x5
144 #define ACLK_160_RATIO 0x4
145 #define ACLK_100_RATIO 0x7
146 #define ACLK_200_RATIO 0x3
151 | (ACLK_200_RATIO << 0))
154 #define MUX_GDL_SEL_SCLKMPLL 0x0
155 #define MUX_GDL_SEL_SCLKAPLL 0x1
159 #define GPL_RATIO 0x1
160 #define GDL_RATIO 0x3
164 #define MUX_GDR_SEL_SCLKMPLL 0x0
165 #define MUX_GDR_SEL_SCLKAPLL 0x1
169 #define GPR_RATIO 0x1
170 #define GDR_RATIO 0x3
174 #define SATA_SEL_SCLKMPLL 0
177 #define MMC_SEL_XXTI 0
197 | (MMCC0_SEL << 0))
199 /* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
201 #define MMC0_RATIO 0xF
202 #define MMC0_PRE_RATIO 0x0
203 #define MMC1_RATIO 0xF
204 #define MMC1_PRE_RATIO 0x0
208 | (MMC0_RATIO << 0))
211 #define MMC2_RATIO 0xF
212 #define MMC2_PRE_RATIO 0x0
213 #define MMC3_RATIO 0xF
214 #define MMC3_PRE_RATIO 0x0
218 | (MMC2_RATIO << 0))
221 #define MMC4_RATIO 0xF
222 #define MMC4_PRE_RATIO 0x0
224 | (MMC4_RATIO << 0))
227 #define UART_SEL_XXTI 0
246 | (UART0_SEL << 0))
248 /* SCLK_UART[0-4] = MOUTUART[0-4]/(UART[0-4]_RATIO + 1) */
259 | (UART0_RATIO << 0))
281 | (FIMC0_LCLK_SEL << 0))
292 | (FIMC0_LCLK_RATIO << 0))
296 #define MFC_SEL_MPLL 0
297 #define MOUTMFC_0 0
309 #define G3D_SEL_MPLL 0
310 #define MOUTG3D_0 0
328 | (FIMD_SEL_SCLKMPLL << 0))
336 #define PLL_LOCKTIME 0x1C20
339 #define DISABLE 0
344 | (sdiv << 0))
347 #define APLL_MDIV 0xFA
348 #define APLL_PDIV 0x6
349 #define APLL_SDIV 0x1
353 #define APLL_AFC_ENB 0x1
354 #define APLL_AFC 0xC
355 #define APLL_CON1_VAL ((APLL_AFC_ENB << 31) | (APLL_AFC << 0))
358 #define MPLL_MDIV 0xC8
359 #define MPLL_PDIV 0x6
360 #define MPLL_SDIV 0x1
364 #define MPLL_AFC_ENB 0x0
365 #define MPLL_AFC 0x1C
366 #define MPLL_CON1_VAL ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0))
369 #define EPLL_MDIV 0x30
370 #define EPLL_PDIV 0x3
371 #define EPLL_SDIV 0x2
375 #define EPLL_K 0x0
376 #define EPLL_CON1_VAL (EPLL_K >> 0)
379 #define VPLL_MDIV 0x35
380 #define VPLL_PDIV 0x3
381 #define VPLL_SDIV 0x2
386 #define VPLL_SEL_PF_DN_SPREAD 0x0
387 #define VPLL_MRR 0x11
388 #define VPLL_MFR 0x0
389 #define VPLL_K 0x400
394 | (VPLL_K << 0))
397 #define DIRECT_CMD_NOP 0x07000000
398 #define DIRECT_CMD_ZQ 0x0a000000
401 #define CTRL_START (1 << 0)
427 #define APB_SFR_INTERLEAVE_CONF_OFFSET 0x400
428 #define APB_SFR_ARBRITATION_CONF_OFFSET 0xC00
429 #define ABP_SFR_SLV_ADDRMAP_CONF_OFFSET 0x800
430 #define ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET 0x808
431 #define ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET 0x810
432 #define ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET 0x818
433 #define ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET 0x820
434 #define ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET 0x828
435 #define ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET 0x830
438 /* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
439 #define APB_SFR_INTERLEAVE_CONF_VAL 0x20001507
440 #define APB_SFR_ARBRITATION_CONF_VAL 0x00000001
443 #define INTERLEAVE_ADDR_MAP_START_ADDR 0x40000000
444 #define INTERLEAVE_ADDR_MAP_END_ADDR 0xbfffffff
445 #define INTERLEAVE_ADDR_MAP_EN 0x00000001
448 /* Interleave_bit0: 0xC*/
449 #define APB_SFR_INTERLEAVE_CONF_VAL 0x0000000c
452 /* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0xc */
453 #define APB_SFR_INTERLEAVE_CONF_VAL 0x2000150c
455 #define SLAVE0_SINGLE_ADDR_MAP_START_ADDR 0x40000000
456 #define SLAVE0_SINGLE_ADDR_MAP_END_ADDR 0x7fffffff
457 #define SLAVE1_SINGLE_ADDR_MAP_START_ADDR 0x80000000
458 #define SLAVE1_SINGLE_ADDR_MAP_END_ADDR 0xbfffffff
460 #define APB_SFR_SLV_ADDR_MAP_CONF_VAL 0x00000006
465 #define DIRECT_CMD1 0x00020000
466 #define DIRECT_CMD2 0x00030000
467 #define DIRECT_CMD3 0x00010002
468 #define DIRECT_CMD4 0x00000328
470 #define CTRL_ZQ_MODE_NOTERM (0x1 << 0)
471 #define CTRL_ZQ_START (0x1 << 1)
472 #define CTRL_ZQ_DIV (0 << 4)
473 #define CTRL_ZQ_MODE_DDS (0x7 << 8)
474 #define CTRL_ZQ_MODE_TERM (0x2 << 11)
475 #define CTRL_ZQ_FORCE_IMPN (0x5 << 14)
476 #define CTRL_ZQ_FORCE_IMPP (0x6 << 17)
477 #define CTRL_DCC (0xE38 << 20)
483 #define ASYNC (0 << 0)
487 #define AREF_DISABLE (0 << 5)
488 #define DRV_TYPE_DISABLE (0 << 6)
489 #define CHIP0_NOT_EMPTY (0 << 8)
490 #define CHIP1_NOT_EMPTY (0 << 9)
491 #define DQ_SWAP_DISABLE (0 << 10)
492 #define QOS_FAST_DISABLE (0 << 11)
493 #define RD_FETCH (0x3 << 12)
494 #define TIMEOUT_LEVEL0 (0xFFF << 16)
501 #define CLK_STOP_DISABLE (0 << 1)
502 #define DPWRDN_DISABLE (0 << 2)
503 #define DPWRDN_TYPE (0 << 3)
504 #define TP_DISABLE (0 << 4)
505 #define DSREF_DIABLE (0 << 5)
507 #define MEM_TYPE_DDR3 (0x6 << 8)
508 #define MEM_WIDTH_32 (0x2 << 12)
510 #define BL_8 (0x3 << 20)
517 #define CHIP_BANK_8 (0x3 << 0)
518 #define CHIP_ROW_14 (0x2 << 4)
519 #define CHIP_COL_10 (0x3 << 8)
521 #define CHIP_MASK (0xe0 << 16)
523 #define CHIP0_BASE (0x40 << 24)
524 #define CHIP1_BASE (0x60 << 24)
526 #define CHIP0_BASE (0x20 << 24)
527 #define CHIP1_BASE (0x40 << 24)
534 #define TP_CNT (0xff << 24)
537 #define CTRL_OFF (0 << 0)
538 #define CTRL_DLL_OFF (0 << 1)
539 #define CTRL_HALF (0 << 2)
541 #define DQS_DELAY (0 << 4)
542 #define CTRL_START_POINT (0x10 << 8)
543 #define CTRL_INC (0x10 << 16)
544 #define CTRL_FORCE (0x71 << 24)
549 #define CTRL_SHIFTC (0x6 << 0)
557 #define CONTROL2_VAL 0x00000000
560 #define TIMINGREF_VAL 0x000000BB
561 #define TIMINGROW_VAL 0x4046654f
562 #define TIMINGDATA_VAL 0x46400506
563 #define TIMINGPOWER_VAL 0x52000A3C
565 #define TIMINGREF_VAL 0x000000BC
567 #define TIMINGROW_VAL 0x3545548d
568 #define TIMINGDATA_VAL 0x45430506
569 #define TIMINGPOWER_VAL 0x4439033c
572 #define TIMINGROW_VAL 0x45430506
573 #define TIMINGDATA_VAL 0x56500506
574 #define TIMINGPOWER_VAL 0x5444033d