Lines Matching +full:0 +full:x100000
56 writel((mem.control1 | (0 << mem.dll_resync)), in phy_control_reset()
59 writel((mem.control0 | (0 << mem.dll_on)), in phy_control_reset()
69 unsigned long mask = 0; in dmc_config_mrs()
74 for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) { in dmc_config_mrs()
95 sdelay(0x100000); in dmc_init()
102 phy_control_reset(0, dmc); in dmc_init()
140 sdelay(0x100000); in dmc_init()
143 dmc_config_mrs(dmc, 0); in dmc_init()
144 sdelay(0x100000); in dmc_init()
148 sdelay(0x100000); in dmc_init()
151 sdelay(0x100000); in dmc_init()
155 sdelay(0x100000); in dmc_init()
159 sdelay(0x100000); in dmc_init()
162 sdelay(0x100000); in dmc_init()
175 * 0: full_sync in mem_ctrl_init()
179 /* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */ in mem_ctrl_init()