36 int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)  in ddr3_mem_ctrl_init()  argument
52 	val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) |  in ddr3_mem_ctrl_init()
53 		(mem->impedance << CA_CKE_DRVR_DS_OFFSET) |  in ddr3_mem_ctrl_init()
54 		(mem->impedance << CA_CS_DRVR_DS_OFFSET) |  in ddr3_mem_ctrl_init()
55 		(mem->impedance << CA_ADR_DRVR_DS_OFFSET);  in ddr3_mem_ctrl_init()
60 	val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |  in ddr3_mem_ctrl_init()
61 		(mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);  in ddr3_mem_ctrl_init()
66 	if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16,  in ddr3_mem_ctrl_init()
71 	writel(mem->phy0_pulld_dqs, &phy0_ctrl->phy_con14);  in ddr3_mem_ctrl_init()
72 	writel(mem->phy1_pulld_dqs, &phy1_ctrl->phy_con14);  in ddr3_mem_ctrl_init()
74 	writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)  in ddr3_mem_ctrl_init()
75 		| (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT),  in ddr3_mem_ctrl_init()
81 	writel(mem->phy0_dqs, &phy0_ctrl->phy_con4);  in ddr3_mem_ctrl_init()
82 	writel(mem->phy1_dqs, &phy1_ctrl->phy_con4);  in ddr3_mem_ctrl_init()
84 	writel(mem->phy0_dq, &phy0_ctrl->phy_con6);  in ddr3_mem_ctrl_init()
85 	writel(mem->phy1_dq, &phy1_ctrl->phy_con6);  in ddr3_mem_ctrl_init()
87 	writel(mem->phy0_tFS, &phy0_ctrl->phy_con10);  in ddr3_mem_ctrl_init()
88 	writel(mem->phy1_tFS, &phy1_ctrl->phy_con10);  in ddr3_mem_ctrl_init()
90 	val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) |  in ddr3_mem_ctrl_init()
91 		(mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |  in ddr3_mem_ctrl_init()
92 		(mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |  in ddr3_mem_ctrl_init()
93 		(mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);  in ddr3_mem_ctrl_init()
98 	writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),  in ddr3_mem_ctrl_init()
100 	writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),  in ddr3_mem_ctrl_init()
105 	writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),  in ddr3_mem_ctrl_init()
109 	writel(mem->iv_size, &dmc->ivcontrol);  in ddr3_mem_ctrl_init()
111 	writel(mem->memconfig, &dmc->memconfig0);  in ddr3_mem_ctrl_init()
112 	writel(mem->memconfig, &dmc->memconfig1);  in ddr3_mem_ctrl_init()
113 	writel(mem->membaseconfig0, &dmc->membaseconfig0);  in ddr3_mem_ctrl_init()
114 	writel(mem->membaseconfig1, &dmc->membaseconfig1);  in ddr3_mem_ctrl_init()
117 	writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,  in ddr3_mem_ctrl_init()
121 	writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |  in ddr3_mem_ctrl_init()
122 		mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT,  in ddr3_mem_ctrl_init()
128 	writel(mem->timing_ref, &dmc->timingref);  in ddr3_mem_ctrl_init()
129 	writel(mem->timing_row, &dmc->timingrow);  in ddr3_mem_ctrl_init()
130 	writel(mem->timing_data, &dmc->timingdata);  in ddr3_mem_ctrl_init()
131 	writel(mem->timing_power, &dmc->timingpower);  in ddr3_mem_ctrl_init()
134 	dmc_config_prech(mem, &dmc->directcmd);  in ddr3_mem_ctrl_init()
137 	dmc_config_mrs(mem, &dmc->directcmd);  in ddr3_mem_ctrl_init()
139 	if (mem->gate_leveling_enable) {  in ddr3_mem_ctrl_init()
156 		val = (mem->ctrl_start_point <<  in ddr3_mem_ctrl_init()
158 			(mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |  in ddr3_mem_ctrl_init()
159 			(mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) |  in ddr3_mem_ctrl_init()
160 			(mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |  in ddr3_mem_ctrl_init()
161 			(mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);  in ddr3_mem_ctrl_init()
202 		val = (mem->ctrl_start_point <<  in ddr3_mem_ctrl_init()
204 			(mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |  in ddr3_mem_ctrl_init()
205 			(mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) |  in ddr3_mem_ctrl_init()
206 			(mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |  in ddr3_mem_ctrl_init()
207 			(mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |  in ddr3_mem_ctrl_init()
208 			(mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);  in ddr3_mem_ctrl_init()
216 	dmc_config_prech(mem, &dmc->directcmd);  in ddr3_mem_ctrl_init()
218 	writel(mem->memcontrol, &dmc->memcontrol);  in ddr3_mem_ctrl_init()
221 	writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)  in ddr3_mem_ctrl_init()
222 		| (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol);  in ddr3_mem_ctrl_init()
441 int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)  in ddr3_mem_ctrl_init()  argument
469 		mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_2;  in ddr3_mem_ctrl_init()
470 		mem->chips_per_channel = 2;  in ddr3_mem_ctrl_init()
471 		mem->chips_to_configure = 2;  in ddr3_mem_ctrl_init()
474 		mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_1;  in ddr3_mem_ctrl_init()
503 	val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |  in ddr3_mem_ctrl_init()
504 		(mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);  in ddr3_mem_ctrl_init()
530 	if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16,  in ddr3_mem_ctrl_init()
539 	val |= mem->phy0_pulld_dqs;  in ddr3_mem_ctrl_init()
542 	val |= mem->phy1_pulld_dqs;  in ddr3_mem_ctrl_init()
549 	writel(mem->concontrol |  in ddr3_mem_ctrl_init()
550 		(mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |  in ddr3_mem_ctrl_init()
551 		(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),  in ddr3_mem_ctrl_init()
553 	writel(mem->concontrol |  in ddr3_mem_ctrl_init()
554 		(mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |  in ddr3_mem_ctrl_init()
555 		(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),  in ddr3_mem_ctrl_init()
593 	writel(mem->memconfig, &tzasc0->memconfig0);  in ddr3_mem_ctrl_init()
594 	writel(mem->memconfig, &tzasc1->memconfig0);  in ddr3_mem_ctrl_init()
595 	writel(mem->memconfig, &tzasc0->memconfig1);  in ddr3_mem_ctrl_init()
596 	writel(mem->memconfig, &tzasc1->memconfig1);  in ddr3_mem_ctrl_init()
599 	writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,  in ddr3_mem_ctrl_init()
601 	writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,  in ddr3_mem_ctrl_init()
608 	writel(mem->timing_ref, &drex0->timingref);  in ddr3_mem_ctrl_init()
609 	writel(mem->timing_ref, &drex1->timingref);  in ddr3_mem_ctrl_init()
610 	writel(mem->timing_row, &drex0->timingrow0);  in ddr3_mem_ctrl_init()
611 	writel(mem->timing_row, &drex1->timingrow0);  in ddr3_mem_ctrl_init()
612 	writel(mem->timing_data, &drex0->timingdata0);  in ddr3_mem_ctrl_init()
613 	writel(mem->timing_data, &drex1->timingdata0);  in ddr3_mem_ctrl_init()
614 	writel(mem->timing_power, &drex0->timingpower0);  in ddr3_mem_ctrl_init()
615 	writel(mem->timing_power, &drex1->timingpower0);  in ddr3_mem_ctrl_init()
624 		dmc_config_mrs(mem, &drex0->directcmd);  in ddr3_mem_ctrl_init()
625 		dmc_config_mrs(mem, &drex1->directcmd);  in ddr3_mem_ctrl_init()
680 			for (chip = 0; chip < mem->chips_to_configure; chip++) {  in ddr3_mem_ctrl_init()
691 	if (mem->gate_leveling_enable) {  in ddr3_mem_ctrl_init()
724 		for (chip = 0; chip < mem->chips_to_configure; chip++) {  in ddr3_mem_ctrl_init()
779 		for (chip = 0; chip < mem->chips_to_configure; chip++) {  in ddr3_mem_ctrl_init()
817 	dmc_config_prech(mem, &drex0->directcmd);  in ddr3_mem_ctrl_init()
818 	dmc_config_prech(mem, &drex1->directcmd);  in ddr3_mem_ctrl_init()
820 	writel(mem->memcontrol, &drex0->memcontrol);  in ddr3_mem_ctrl_init()
821 	writel(mem->memcontrol, &drex1->memcontrol);  in ddr3_mem_ctrl_init()
828 	writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |  in ddr3_mem_ctrl_init()
829 		(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|  in ddr3_mem_ctrl_init()
832 	writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |  in ddr3_mem_ctrl_init()
833 		(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|  in ddr3_mem_ctrl_init()