448 	struct exynos5420_dmc *drex0, *drex1;  in ddr3_mem_ctrl_init()  local
460 	drex1 = (struct exynos5420_dmc *)(samsung_get_base_dmc_ctrl()  in ddr3_mem_ctrl_init()
547 	writel(val, &drex1->phycontrol0);  in ddr3_mem_ctrl_init()
556 		&drex1->concontrol);  in ddr3_mem_ctrl_init()
562 		val = readl(&drex1->phystatus);  in ddr3_mem_ctrl_init()
566 	clrbits_le32(&drex1->concontrol, DFI_INIT_START);  in ddr3_mem_ctrl_init()
569 	update_reset_dll(&drex1->phycontrol0, DDR_MODE_DDR3);  in ddr3_mem_ctrl_init()
602 	       &drex1->prechconfig0);  in ddr3_mem_ctrl_init()
609 	writel(mem->timing_ref, &drex1->timingref);  in ddr3_mem_ctrl_init()
611 	writel(mem->timing_row, &drex1->timingrow0);  in ddr3_mem_ctrl_init()
613 	writel(mem->timing_data, &drex1->timingdata0);  in ddr3_mem_ctrl_init()
615 	writel(mem->timing_power, &drex1->timingpower0);  in ddr3_mem_ctrl_init()
625 		dmc_config_mrs(mem, &drex1->directcmd);  in ddr3_mem_ctrl_init()
686 				       &drex1->directcmd);  in ddr3_mem_ctrl_init()
728 			       &drex1->directcmd);  in ddr3_mem_ctrl_init()
760 		writel(CTRL_RDLVL_GATE_ENABLE, &drex1->rdlvl_config);  in ddr3_mem_ctrl_init()
762 		while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO) !=  in ddr3_mem_ctrl_init()
773 		writel(CTRL_RDLVL_GATE_DISABLE, &drex1->rdlvl_config);  in ddr3_mem_ctrl_init()
783 			       &drex1->directcmd);  in ddr3_mem_ctrl_init()
818 	dmc_config_prech(mem, &drex1->directcmd);  in ddr3_mem_ctrl_init()
821 	writel(mem->memcontrol, &drex1->memcontrol);  in ddr3_mem_ctrl_init()
835 		&drex1->concontrol);  in ddr3_mem_ctrl_init()
843 	setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG);  in ddr3_mem_ctrl_init()
860 	val = readl(&drex1->concontrol);  in ddr3_mem_ctrl_init()
862 	writel(val, &drex1->concontrol);  in ddr3_mem_ctrl_init()