448 	struct exynos5420_dmc *drex0, *drex1;  in ddr3_mem_ctrl_init()  local
459 	drex0 = (struct exynos5420_dmc *)samsung_get_base_dmc_ctrl();  in ddr3_mem_ctrl_init()
546 	writel(val, &drex0->phycontrol0);  in ddr3_mem_ctrl_init()
552 		&drex0->concontrol);  in ddr3_mem_ctrl_init()
559 		val = readl(&drex0->phystatus);  in ddr3_mem_ctrl_init()
565 	clrbits_le32(&drex0->concontrol, DFI_INIT_START);  in ddr3_mem_ctrl_init()
568 	update_reset_dll(&drex0->phycontrol0, DDR_MODE_DDR3);  in ddr3_mem_ctrl_init()
600 	       &drex0->prechconfig0);  in ddr3_mem_ctrl_init()
608 	writel(mem->timing_ref, &drex0->timingref);  in ddr3_mem_ctrl_init()
610 	writel(mem->timing_row, &drex0->timingrow0);  in ddr3_mem_ctrl_init()
612 	writel(mem->timing_data, &drex0->timingdata0);  in ddr3_mem_ctrl_init()
614 	writel(mem->timing_power, &drex0->timingpower0);  in ddr3_mem_ctrl_init()
624 		dmc_config_mrs(mem, &drex0->directcmd);  in ddr3_mem_ctrl_init()
683 				       &drex0->directcmd);  in ddr3_mem_ctrl_init()
726 			       &drex0->directcmd);  in ddr3_mem_ctrl_init()
745 		writel(CTRL_RDLVL_GATE_ENABLE, &drex0->rdlvl_config);  in ddr3_mem_ctrl_init()
747 		while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO) !=  in ddr3_mem_ctrl_init()
758 		writel(CTRL_RDLVL_GATE_DISABLE, &drex0->rdlvl_config);  in ddr3_mem_ctrl_init()
781 			       &drex0->directcmd);  in ddr3_mem_ctrl_init()
817 	dmc_config_prech(mem, &drex0->directcmd);  in ddr3_mem_ctrl_init()
820 	writel(mem->memcontrol, &drex0->memcontrol);  in ddr3_mem_ctrl_init()
831 		&drex0->concontrol);  in ddr3_mem_ctrl_init()
842 	setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG);  in ddr3_mem_ctrl_init()
857 	val = readl(&drex0->concontrol);  in ddr3_mem_ctrl_init()
859 	writel(val, &drex0->concontrol);  in ddr3_mem_ctrl_init()