14 #include <asm/arch/dmc.h>
40 	struct exynos5_dmc *dmc;  in ddr3_mem_ctrl_init()  local
46 	dmc = (struct exynos5_dmc *)samsung_get_base_dmc_ctrl();  in ddr3_mem_ctrl_init()
76 		&dmc->concontrol);  in ddr3_mem_ctrl_init()
78 	update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);  in ddr3_mem_ctrl_init()
103 	update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);  in ddr3_mem_ctrl_init()
106 	       &dmc->concontrol);  in ddr3_mem_ctrl_init()
109 	writel(mem->iv_size, &dmc->ivcontrol);  in ddr3_mem_ctrl_init()
111 	writel(mem->memconfig, &dmc->memconfig0);  in ddr3_mem_ctrl_init()
112 	writel(mem->memconfig, &dmc->memconfig1);  in ddr3_mem_ctrl_init()
113 	writel(mem->membaseconfig0, &dmc->membaseconfig0);  in ddr3_mem_ctrl_init()
114 	writel(mem->membaseconfig1, &dmc->membaseconfig1);  in ddr3_mem_ctrl_init()
118 	       &dmc->prechconfig);  in ddr3_mem_ctrl_init()
123 		&dmc->pwrdnconfig);  in ddr3_mem_ctrl_init()
128 	writel(mem->timing_ref, &dmc->timingref);  in ddr3_mem_ctrl_init()
129 	writel(mem->timing_row, &dmc->timingrow);  in ddr3_mem_ctrl_init()
130 	writel(mem->timing_data, &dmc->timingdata);  in ddr3_mem_ctrl_init()
131 	writel(mem->timing_power, &dmc->timingpower);  in ddr3_mem_ctrl_init()
134 	dmc_config_prech(mem, &dmc->directcmd);  in ddr3_mem_ctrl_init()
137 	dmc_config_mrs(mem, &dmc->directcmd);  in ddr3_mem_ctrl_init()
183 		writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config);  in ddr3_mem_ctrl_init()
185 		while ((readl(&dmc->phystatus) &  in ddr3_mem_ctrl_init()
197 		writel(CTRL_RDLVL_GATE_DISABLE, &dmc->rdlvl_config);  in ddr3_mem_ctrl_init()
212 		update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);  in ddr3_mem_ctrl_init()
216 	dmc_config_prech(mem, &dmc->directcmd);  in ddr3_mem_ctrl_init()
218 	writel(mem->memcontrol, &dmc->memcontrol);  in ddr3_mem_ctrl_init()
220 	/* Set DMC Concontrol and enable auto-refresh counter */  in ddr3_mem_ctrl_init()
222 		| (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol);  in ddr3_mem_ctrl_init()
254  * @param ch			DMC channel number
824 	 * Set DMC Concontrol: Enable auto-refresh counter, provide  in ddr3_mem_ctrl_init()
838 	 * Enable Clock Gating Control for DMC  in ddr3_mem_ctrl_init()
839 	 * this saves around 25 mw dmc power as compared to the power  in ddr3_mem_ctrl_init()
852 	 * once at DMC init time and not updated later when we change the MIF  in ddr3_mem_ctrl_init()