141 	if (pllreg == EPLL || pllreg == RPLL) {  in exynos_get_pll_clk()
199 	case EPLL:  in exynos4_get_pll_clk()
229 	case EPLL:  in exynos4x12_get_pll_clk()
260 	case EPLL:  in exynos5_get_pll_clk()
318 	case EPLL:  in exynos542x_get_pll_clk()
441 		sclk = exynos5_get_pll_clk(EPLL);  in exynos5_get_periph_rate()
535 		sclk = exynos542x_get_pll_clk(EPLL);  in exynos542x_get_periph_rate()
655 			sclk = get_pll_clk(EPLL);  in exynos4_get_pwm_clk()
716 		sclk = get_pll_clk(EPLL);  in exynos4_get_uart_clk()
762 		sclk = get_pll_clk(EPLL);  in exynos4x12_get_uart_clk()
798 		sclk = get_pll_clk(EPLL);  in exynos4_get_mmc_clk()
936 		sclk = get_pll_clk(EPLL);  in exynos4_get_lcd_clk()
978 		sclk = get_pll_clk(EPLL);  in exynos5_get_lcd_clk()
1050 		const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL,  in exynos5800_get_lcd_clk()