5  * SPDX-License-Identifier:	GPL-2.0+
11 #include <asm/arch/clk.h>
33 	{PERIPH_ID_UART0,	0xf,	0xf,	-1,	0,	0,	-1},
34 	{PERIPH_ID_UART1,	0xf,	0xf,	-1,	4,	4,	-1},
35 	{PERIPH_ID_UART2,	0xf,	0xf,	-1,	8,	8,	-1},
36 	{PERIPH_ID_UART3,	0xf,	0xf,	-1,	12,	12,	-1},
37 	{PERIPH_ID_I2C0,	-1,	0x7,	0x7,	-1,	24,	0},
38 	{PERIPH_ID_I2C1,	-1,	0x7,	0x7,	-1,	24,	0},
39 	{PERIPH_ID_I2C2,	-1,	0x7,	0x7,	-1,	24,	0},
40 	{PERIPH_ID_I2C3,	-1,	0x7,	0x7,	-1,	24,	0},
41 	{PERIPH_ID_I2C4,	-1,	0x7,	0x7,	-1,	24,	0},
42 	{PERIPH_ID_I2C5,	-1,	0x7,	0x7,	-1,	24,	0},
43 	{PERIPH_ID_I2C6,	-1,	0x7,	0x7,	-1,	24,	0},
44 	{PERIPH_ID_I2C7,	-1,	0x7,	0x7,	-1,	24,	0},
57 	{PERIPH_ID_PWM0,	0xf,	0xf,	-1,	24,	0,	-1},
58 	{PERIPH_ID_PWM1,	0xf,	0xf,	-1,	24,	0,	-1},
59 	{PERIPH_ID_PWM2,	0xf,	0xf,	-1,	24,	0,	-1},
60 	{PERIPH_ID_PWM3,	0xf,	0xf,	-1,	24,	0,	-1},
61 	{PERIPH_ID_PWM4,	0xf,	0xf,	-1,	24,	0,	-1},
63 	{PERIPH_ID_NONE,	-1,	-1,	-1,	-1,	-1,	-1},
68 	{PERIPH_ID_UART0,	0xf,	0xf,	-1,	4,	8,	-1},
69 	{PERIPH_ID_UART1,	0xf,	0xf,	-1,	8,	12,	-1},
70 	{PERIPH_ID_UART2,	0xf,	0xf,	-1,	12,	16,	-1},
71 	{PERIPH_ID_UART3,	0xf,	0xf,	-1,	16,	20,	-1},
72 	{PERIPH_ID_I2C0,	-1,	0x3f,	-1,	-1,	8,	-1},
73 	{PERIPH_ID_I2C1,	-1,	0x3f,	-1,	-1,	8,	-1},
74 	{PERIPH_ID_I2C2,	-1,	0x3f,	-1,	-1,	8,	-1},
75 	{PERIPH_ID_I2C3,	-1,	0x3f,	-1,	-1,	8,	-1},
76 	{PERIPH_ID_I2C4,	-1,	0x3f,	-1,	-1,	8,	-1},
77 	{PERIPH_ID_I2C5,	-1,	0x3f,	-1,	-1,	8,	-1},
78 	{PERIPH_ID_I2C6,	-1,	0x3f,	-1,	-1,	8,	-1},
79 	{PERIPH_ID_I2C7,	-1,	0x3f,	-1,	-1,	8,	-1},
83 	{PERIPH_ID_SDMMC0,	0x7,	0x3ff,	-1,	8,	0,	-1},
84 	{PERIPH_ID_SDMMC1,	0x7,	0x3ff,	-1,	12,	10,	-1},
85 	{PERIPH_ID_SDMMC2,	0x7,	0x3ff,	-1,	16,	20,	-1},
86 	{PERIPH_ID_I2C8,	-1,	0x3f,	-1,	-1,	8,	-1},
87 	{PERIPH_ID_I2C9,	-1,	0x3f,	-1,	-1,	8,	-1},
92 	{PERIPH_ID_PWM0,	0xf,	0xf,	-1,	24,	28,	-1},
93 	{PERIPH_ID_PWM1,	0xf,	0xf,	-1,	24,	28,	-1},
94 	{PERIPH_ID_PWM2,	0xf,	0xf,	-1,	24,	28,	-1},
95 	{PERIPH_ID_PWM3,	0xf,	0xf,	-1,	24,	28,	-1},
96 	{PERIPH_ID_PWM4,	0xf,	0xf,	-1,	24,	28,	-1},
97 	{PERIPH_ID_I2C10,	-1,	0x3f,	-1,	-1,	8,	-1},
99 	{PERIPH_ID_NONE,	-1,	-1,	-1,	-1,	-1,	-1},
102 /* Epll Clock division values to achive different frequency output */
175 		 * FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1))  in exynos_get_pll_clk()
178 			fout = m * (freq / (p * (1 << (s - 1))));  in exynos_get_pll_clk()
188 	struct exynos4_clock *clk =  in exynos4_get_pll_clk()  local
194 		r = readl(&clk->apll_con0);  in exynos4_get_pll_clk()
197 		r = readl(&clk->mpll_con0);  in exynos4_get_pll_clk()
200 		r = readl(&clk->epll_con0);  in exynos4_get_pll_clk()
201 		k = readl(&clk->epll_con1);  in exynos4_get_pll_clk()
204 		r = readl(&clk->vpll_con0);  in exynos4_get_pll_clk()
205 		k = readl(&clk->vpll_con1);  in exynos4_get_pll_clk()
218 	struct exynos4x12_clock *clk =  in exynos4x12_get_pll_clk()  local
224 		r = readl(&clk->apll_con0);  in exynos4x12_get_pll_clk()
227 		r = readl(&clk->mpll_con0);  in exynos4x12_get_pll_clk()
230 		r = readl(&clk->epll_con0);  in exynos4x12_get_pll_clk()
231 		k = readl(&clk->epll_con1);  in exynos4x12_get_pll_clk()
234 		r = readl(&clk->vpll_con0);  in exynos4x12_get_pll_clk()
235 		k = readl(&clk->vpll_con1);  in exynos4x12_get_pll_clk()
248 	struct exynos5_clock *clk =  in exynos5_get_pll_clk()  local
255 		r = readl(&clk->apll_con0);  in exynos5_get_pll_clk()
258 		r = readl(&clk->mpll_con0);  in exynos5_get_pll_clk()
261 		r = readl(&clk->epll_con0);  in exynos5_get_pll_clk()
262 		k = readl(&clk->epll_con1);  in exynos5_get_pll_clk()
265 		r = readl(&clk->vpll_con0);  in exynos5_get_pll_clk()
266 		k = readl(&clk->vpll_con1);  in exynos5_get_pll_clk()
269 		r = readl(&clk->bpll_con0);  in exynos5_get_pll_clk()
281 		pll_div2_sel = readl(&clk->pll_div2_sel);  in exynos5_get_pll_clk()
293 			fout_sel = -1;  in exynos5_get_pll_clk()
307 	struct exynos5420_clock *clk =  in exynos542x_get_pll_clk()  local
313 		r = readl(&clk->apll_con0);  in exynos542x_get_pll_clk()
316 		r = readl(&clk->mpll_con0);  in exynos542x_get_pll_clk()
319 		r = readl(&clk->epll_con0);  in exynos542x_get_pll_clk()
320 		k = readl(&clk->epll_con1);  in exynos542x_get_pll_clk()
323 		r = readl(&clk->vpll_con0);  in exynos542x_get_pll_clk()
324 		k = readl(&clk->vpll_con1);  in exynos542x_get_pll_clk()
327 		r = readl(&clk->bpll_con0);  in exynos542x_get_pll_clk()
330 		r = readl(&clk->rpll_con0);  in exynos542x_get_pll_clk()
331 		k = readl(&clk->rpll_con1);  in exynos542x_get_pll_clk()
334 		r = readl(&clk->spll_con0);  in exynos542x_get_pll_clk()
370 	struct exynos5_clock *clk =  in exynos5_get_periph_rate()  local
378 		src = readl(&clk->src_peric0);  in exynos5_get_periph_rate()
379 		div = readl(&clk->div_peric0);  in exynos5_get_periph_rate()
386 		src = readl(&clk->src_peric0);  in exynos5_get_periph_rate()
387 		div = readl(&clk->div_peric3);  in exynos5_get_periph_rate()
390 		src = readl(&clk->src_mau);  in exynos5_get_periph_rate()
391 		div = sub_div = readl(&clk->div_mau);  in exynos5_get_periph_rate()
394 		src = readl(&clk->src_peric1);  in exynos5_get_periph_rate()
395 		div = sub_div = readl(&clk->div_peric1);  in exynos5_get_periph_rate()
398 		src = readl(&clk->src_peric1);  in exynos5_get_periph_rate()
399 		div = sub_div = readl(&clk->div_peric2);  in exynos5_get_periph_rate()
403 		src = readl(&clk->sclk_src_isp);  in exynos5_get_periph_rate()
404 		div = sub_div = readl(&clk->sclk_div_isp);  in exynos5_get_periph_rate()
408 		src = readl(&clk->src_fsys);  in exynos5_get_periph_rate()
409 		div = sub_div = readl(&clk->div_fsys1);  in exynos5_get_periph_rate()
413 		src = readl(&clk->src_fsys);  in exynos5_get_periph_rate()
414 		div = sub_div = readl(&clk->div_fsys2);  in exynos5_get_periph_rate()
425 		div = readl(&clk->div_top1);  in exynos5_get_periph_rate()
426 		sub_div = readl(&clk->div_top0);  in exynos5_get_periph_rate()
430 		return -1;  in exynos5_get_periph_rate()
433 	if (bit_info->src_bit >= 0)  in exynos5_get_periph_rate()
434 		src = (src >> bit_info->src_bit) & bit_info->src_mask;  in exynos5_get_periph_rate()
452 	if (bit_info->div_bit >= 0)  in exynos5_get_periph_rate()
453 		div = (div >> bit_info->div_bit) & bit_info->div_mask;  in exynos5_get_periph_rate()
455 	/* Clock pre-divider ratio for this peripheral */  in exynos5_get_periph_rate()
456 	if (bit_info->prediv_bit >= 0)  in exynos5_get_periph_rate()
457 		sub_div = (sub_div >> bit_info->prediv_bit)  in exynos5_get_periph_rate()
458 			  & bit_info->prediv_mask;  in exynos5_get_periph_rate()
469 	struct exynos5420_clock *clk =  in exynos542x_get_periph_rate()  local
482 		src = readl(&clk->src_peric0);  in exynos542x_get_periph_rate()
483 		div = readl(&clk->div_peric0);  in exynos542x_get_periph_rate()
488 		src = readl(&clk->src_peric1);  in exynos542x_get_periph_rate()
489 		div = readl(&clk->div_peric1);  in exynos542x_get_periph_rate()
490 		sub_div = readl(&clk->div_peric4);  in exynos542x_get_periph_rate()
494 		src = readl(&clk->src_isp);  in exynos542x_get_periph_rate()
495 		div = readl(&clk->div_isp1);  in exynos542x_get_periph_rate()
496 		sub_div = readl(&clk->div_isp1);  in exynos542x_get_periph_rate()
502 		src = readl(&clk->src_fsys);  in exynos542x_get_periph_rate()
503 		div = readl(&clk->div_fsys1);  in exynos542x_get_periph_rate()
517 		div = readl(&clk->div_top1);  in exynos542x_get_periph_rate()
521 		return -1;  in exynos542x_get_periph_rate()
524 	if (bit_info->src_bit >= 0)  in exynos542x_get_periph_rate()
525 		src = (src >> bit_info->src_bit) & bit_info->src_mask;  in exynos542x_get_periph_rate()
546 	if (bit_info->div_bit >= 0)  in exynos542x_get_periph_rate()
547 		div = (div >> bit_info->div_bit) & bit_info->div_mask;  in exynos542x_get_periph_rate()
549 	/* Clock pre-divider ratio for this peripheral */  in exynos542x_get_periph_rate()
550 	if (bit_info->prediv_bit >= 0)  in exynos542x_get_periph_rate()
551 		sub_div = (sub_div >> bit_info->prediv_bit)  in exynos542x_get_periph_rate()
552 			  & bit_info->prediv_mask;  in exynos542x_get_periph_rate()
572 	struct exynos4_clock *clk =  in exynos4_get_arm_clk()  local
579 	div = readl(&clk->div_cpu0);  in exynos4_get_arm_clk()
594 	struct exynos4x12_clock *clk =  in exynos4x12_get_arm_clk()  local
601 	div = readl(&clk->div_cpu0);  in exynos4x12_get_arm_clk()
616 	struct exynos5_clock *clk =  in exynos5_get_arm_clk()  local
623 	div = readl(&clk->div_cpu0);  in exynos5_get_arm_clk()
638 	struct exynos4_clock *clk =  in exynos4_get_pwm_clk()  local
641 	unsigned int sel;  in exynos4_get_pwm_clk()  local
649 		sel = readl(&clk->src_peril0);  in exynos4_get_pwm_clk()
650 		sel = (sel >> 24) & 0xf;  in exynos4_get_pwm_clk()
652 		if (sel == 0x6)  in exynos4_get_pwm_clk()
654 		else if (sel == 0x7)  in exynos4_get_pwm_clk()
656 		else if (sel == 0x8)  in exynos4_get_pwm_clk()
665 		ratio = readl(&clk->div_peril3);  in exynos4_get_pwm_clk()
695 	struct exynos4_clock *clk =  in exynos4_get_uart_clk()  local
698 	unsigned int sel;  in exynos4_get_uart_clk()  local
710 	sel = readl(&clk->src_peril0);  in exynos4_get_uart_clk()
711 	sel = (sel >> (dev_index << 2)) & 0xf;  in exynos4_get_uart_clk()
713 	if (sel == 0x6)  in exynos4_get_uart_clk()
715 	else if (sel == 0x7)  in exynos4_get_uart_clk()
717 	else if (sel == 0x8)  in exynos4_get_uart_clk()
731 	ratio = readl(&clk->div_peril0);  in exynos4_get_uart_clk()
742 	struct exynos4x12_clock *clk =  in exynos4x12_get_uart_clk()  local
745 	unsigned int sel;  in exynos4x12_get_uart_clk()  local
756 	sel = readl(&clk->src_peril0);  in exynos4x12_get_uart_clk()
757 	sel = (sel >> (dev_index << 2)) & 0xf;  in exynos4x12_get_uart_clk()
759 	if (sel == 0x6)  in exynos4x12_get_uart_clk()
761 	else if (sel == 0x7)  in exynos4x12_get_uart_clk()
763 	else if (sel == 0x8)  in exynos4x12_get_uart_clk()
776 	ratio = readl(&clk->div_peril0);  in exynos4x12_get_uart_clk()
786 	struct exynos4_clock *clk =  in exynos4_get_mmc_clk()  local
789 	unsigned int sel, ratio, pre_ratio;  in exynos4_get_mmc_clk()  local
792 	sel = readl(&clk->src_fsys);  in exynos4_get_mmc_clk()
793 	sel = (sel >> (dev_index << 2)) & 0xf;  in exynos4_get_mmc_clk()
795 	if (sel == 0x6)  in exynos4_get_mmc_clk()
797 	else if (sel == 0x7)  in exynos4_get_mmc_clk()
799 	else if (sel == 0x8)  in exynos4_get_mmc_clk()
807 		ratio = readl(&clk->div_fsys1);  in exynos4_get_mmc_clk()
808 		pre_ratio = readl(&clk->div_fsys1);  in exynos4_get_mmc_clk()
812 		ratio = readl(&clk->div_fsys2);  in exynos4_get_mmc_clk()
813 		pre_ratio = readl(&clk->div_fsys2);  in exynos4_get_mmc_clk()
816 		ratio = readl(&clk->div_fsys3);  in exynos4_get_mmc_clk()
817 		pre_ratio = readl(&clk->div_fsys3);  in exynos4_get_mmc_clk()
836 	struct exynos4_clock *clk =  in exynos4_set_mmc_clk()  local
849 		addr = (unsigned int)&clk->div_fsys1;  in exynos4_set_mmc_clk()
853 		addr = (unsigned int)&clk->div_fsys3;  in exynos4_set_mmc_clk()
854 		dev_index -= 4;  in exynos4_set_mmc_clk()
859 		addr = (unsigned int)&clk->div_fsys2;  in exynos4_set_mmc_clk()
860 		dev_index -= 2;  in exynos4_set_mmc_clk()
871 	struct exynos5_clock *clk =  in exynos5_set_mmc_clk()  local
882 		addr = (unsigned int)&clk->div_fsys1;  in exynos5_set_mmc_clk()
884 		addr = (unsigned int)&clk->div_fsys2;  in exynos5_set_mmc_clk()
885 		dev_index -= 2;  in exynos5_set_mmc_clk()
895 	struct exynos5420_clock *clk =  in exynos5420_set_mmc_clk()  local
906 	addr = (unsigned int)&clk->div_fsys1;  in exynos5420_set_mmc_clk()
915 	struct exynos4_clock *clk =  in exynos4_get_lcd_clk()  local
918 	unsigned int sel;  in exynos4_get_lcd_clk()  local
925 	sel = readl(&clk->src_lcd0);  in exynos4_get_lcd_clk()
926 	sel = sel & 0xf;  in exynos4_get_lcd_clk()
933 	if (sel == 0x6)  in exynos4_get_lcd_clk()
935 	else if (sel == 0x7)  in exynos4_get_lcd_clk()
937 	else if (sel == 0x8)  in exynos4_get_lcd_clk()
946 	ratio = readl(&clk->div_lcd0);  in exynos4_get_lcd_clk()
957 	struct exynos5_clock *clk =  in exynos5_get_lcd_clk()  local
960 	unsigned int sel;  in exynos5_get_lcd_clk()  local
967 	sel = readl(&clk->src_disp1_0);  in exynos5_get_lcd_clk()
968 	sel = sel & 0xf;  in exynos5_get_lcd_clk()
975 	if (sel == 0x6)  in exynos5_get_lcd_clk()
977 	else if (sel == 0x7)  in exynos5_get_lcd_clk()
979 	else if (sel == 0x8)  in exynos5_get_lcd_clk()
988 	ratio = readl(&clk->div_disp1_0);  in exynos5_get_lcd_clk()
998 	struct exynos5420_clock *clk =  in exynos5420_get_lcd_clk()  local
1001 	unsigned int sel;  in exynos5420_get_lcd_clk()  local
1010 	sel = readl(&clk->src_disp10);  in exynos5420_get_lcd_clk()
1011 	sel &= (1 << 4);  in exynos5420_get_lcd_clk()
1013 	if (sel)  in exynos5420_get_lcd_clk()
1022 	ratio = readl(&clk->div_disp10);  in exynos5420_get_lcd_clk()
1032 	struct exynos5420_clock *clk =  in exynos5800_get_lcd_clk()  local
1035 	unsigned int sel;  in exynos5800_get_lcd_clk()  local
1042 	sel = (readl(&clk->src_disp10) >> 4) & 0x7;  in exynos5800_get_lcd_clk()
1044 	if (sel) {  in exynos5800_get_lcd_clk()
1052 		sclk = get_pll_clk(reg_map[sel]);  in exynos5800_get_lcd_clk()
1059 	ratio = readl(&clk->div_disp10) & 0xf;  in exynos5800_get_lcd_clk()
1066 	struct exynos4_clock *clk =  in exynos4_set_lcd_clk()  local
1079 	setbits_le32(&clk->gate_block, 1 << 4);  in exynos4_set_lcd_clk()
1089 	clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6);  in exynos4_set_lcd_clk()
1101 	setbits_le32(&clk->gate_ip_lcd0, 1 << 0);  in exynos4_set_lcd_clk()
1113 	clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1);  in exynos4_set_lcd_clk()
1118 	struct exynos5_clock *clk =  in exynos5_set_lcd_clk()  local
1131 	setbits_le32(&clk->gate_block, 1 << 4);  in exynos5_set_lcd_clk()
1141 	clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6);  in exynos5_set_lcd_clk()
1153 	setbits_le32(&clk->gate_ip_disp1, 1 << 0);  in exynos5_set_lcd_clk()
1165 	clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);  in exynos5_set_lcd_clk()
1170 	struct exynos5420_clock *clk =  in exynos5420_set_lcd_clk()  local
1180 	cfg = readl(&clk->src_disp10);  in exynos5420_set_lcd_clk()
1183 	writel(cfg, &clk->src_disp10);  in exynos5420_set_lcd_clk()
1189 	cfg = readl(&clk->div_disp10);  in exynos5420_set_lcd_clk()
1192 	writel(cfg, &clk->div_disp10);  in exynos5420_set_lcd_clk()
1197 	struct exynos5420_clock *clk =  in exynos5800_set_lcd_clk()  local
1207 	cfg = readl(&clk->src_disp10) | (0x7 << 4);  in exynos5800_set_lcd_clk()
1208 	writel(cfg, &clk->src_disp10);  in exynos5800_set_lcd_clk()
1214 	clrsetbits_le32(&clk->div_disp10, 0xf << 0, 0x0 << 0);  in exynos5800_set_lcd_clk()
1219 	struct exynos4_clock *clk =  in exynos4_set_mipi_clk()  local
1230 	clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12);  in exynos4_set_mipi_clk()
1240 	setbits_le32(&clk->src_mask_lcd0, 0x1 << 12);  in exynos4_set_mipi_clk()
1252 	setbits_le32(&clk->gate_ip_lcd0, 1 << 3);  in exynos4_set_mipi_clk()
1264 	clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16);  in exynos4_set_mipi_clk()
1273 	struct exynos5_clock *clk =  in exynos5_set_epll_clk()  local
1276 	epll_con = readl(&clk->epll_con0);  in exynos5_set_epll_clk()
1289 		return -1;  in exynos5_set_epll_clk()
1299 	 * Required period ( in cycles) to genarate a stable clock output.  in exynos5_set_epll_clk()
1305 	writel(lockcnt, &clk->epll_lock);  in exynos5_set_epll_clk()
1306 	writel(epll_con, &clk->epll_con0);  in exynos5_set_epll_clk()
1307 	writel(epll_con_k, &clk->epll_con1);  in exynos5_set_epll_clk()
1311 	 while (!(readl(&clk->epll_con0) &  in exynos5_set_epll_clk()
1315 			return -1;  in exynos5_set_epll_clk()
1323 	struct exynos5_clock *clk =  in exynos5_set_i2s_clk_source()  local
1328 		setbits_le32(&clk->src_top2, CLK_SRC_MOUT_EPLL);  in exynos5_set_i2s_clk_source()
1329 		clrsetbits_le32(&clk->src_mau, AUDIO0_SEL_MASK,  in exynos5_set_i2s_clk_source()
1333 		clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK,  in exynos5_set_i2s_clk_source()
1336 		return -1;  in exynos5_set_i2s_clk_source()
1345 	struct exynos5_clock *clk =  in exynos5_set_i2s_clk_prescaler()  local
1352 		return -1;  in exynos5_set_i2s_clk_prescaler()
1361 			return -1;  in exynos5_set_i2s_clk_prescaler()
1363 		clrsetbits_le32(&clk->div_mau, AUDIO_0_RATIO_MASK,  in exynos5_set_i2s_clk_prescaler()
1370 			return -1;  in exynos5_set_i2s_clk_prescaler()
1372 		clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK,  in exynos5_set_i2s_clk_prescaler()
1375 		return -1;  in exynos5_set_i2s_clk_prescaler()
1392  * @return best_main_scalar	Main scalar for desired frequency or -1 if none
1400 	int best_main_scalar = -1;  in clock_calc_best_scalar()
1402 	const unsigned int cap = (1 << fine_scalar_bits) - 1;  in clock_calc_best_scalar()
1414 		return -1;  in clock_calc_best_scalar()
1424 		const int error = target_rate - effective_rate;  in clock_calc_best_scalar()
1442 	struct exynos5_clock *clk =  in exynos5_set_spi_clk()  local
1454 		return -1;  in exynos5_set_spi_clk()
1456 	main = main - 1;  in exynos5_set_spi_clk()
1457 	fine = fine - 1;  in exynos5_set_spi_clk()
1461 		reg = &clk->div_peric1;  in exynos5_set_spi_clk()
1466 		reg = &clk->div_peric1;  in exynos5_set_spi_clk()
1471 		reg = &clk->div_peric2;  in exynos5_set_spi_clk()
1476 		reg = &clk->sclk_div_isp;  in exynos5_set_spi_clk()
1481 		reg = &clk->sclk_div_isp;  in exynos5_set_spi_clk()
1488 		return -1;  in exynos5_set_spi_clk()
1499 	struct exynos5420_clock *clk =  in exynos5420_set_spi_clk()  local
1512 		return -1;  in exynos5420_set_spi_clk()
1514 	main = main - 1;  in exynos5420_set_spi_clk()
1515 	fine = fine - 1;  in exynos5420_set_spi_clk()
1519 		reg = &clk->div_peric1;  in exynos5420_set_spi_clk()
1521 		pre_reg = &clk->div_peric4;  in exynos5420_set_spi_clk()
1525 		reg = &clk->div_peric1;  in exynos5420_set_spi_clk()
1527 		pre_reg = &clk->div_peric4;  in exynos5420_set_spi_clk()
1531 		reg = &clk->div_peric1;  in exynos5420_set_spi_clk()
1533 		pre_reg = &clk->div_peric4;  in exynos5420_set_spi_clk()
1537 		reg = &clk->div_isp1;  in exynos5420_set_spi_clk()
1539 		pre_reg = &clk->div_isp1;  in exynos5420_set_spi_clk()
1543 		reg = &clk->div_isp1;  in exynos5420_set_spi_clk()
1545 		pre_reg = &clk->div_isp1;  in exynos5420_set_spi_clk()
1551 		return -1;  in exynos5420_set_spi_clk()
1563 	struct exynos4_clock *clk =  in exynos4_get_i2c_clk()  local
1570 	ratio = (readl(&clk->div_top)) >> 4;  in exynos4_get_i2c_clk()
1646 		return -1;  in get_uart_clk()
1682 		return -1;  in get_mmc_clk()
1692 		div -= 1;  in set_mmc_clk()