Lines Matching +full:0 +full:xf
33 {PERIPH_ID_UART0, 0xf, 0xf, -1, 0, 0, -1},
34 {PERIPH_ID_UART1, 0xf, 0xf, -1, 4, 4, -1},
35 {PERIPH_ID_UART2, 0xf, 0xf, -1, 8, 8, -1},
36 {PERIPH_ID_UART3, 0xf, 0xf, -1, 12, 12, -1},
37 {PERIPH_ID_I2C0, -1, 0x7, 0x7, -1, 24, 0},
38 {PERIPH_ID_I2C1, -1, 0x7, 0x7, -1, 24, 0},
39 {PERIPH_ID_I2C2, -1, 0x7, 0x7, -1, 24, 0},
40 {PERIPH_ID_I2C3, -1, 0x7, 0x7, -1, 24, 0},
41 {PERIPH_ID_I2C4, -1, 0x7, 0x7, -1, 24, 0},
42 {PERIPH_ID_I2C5, -1, 0x7, 0x7, -1, 24, 0},
43 {PERIPH_ID_I2C6, -1, 0x7, 0x7, -1, 24, 0},
44 {PERIPH_ID_I2C7, -1, 0x7, 0x7, -1, 24, 0},
45 {PERIPH_ID_SPI0, 0xf, 0xf, 0xff, 16, 0, 8},
46 {PERIPH_ID_SPI1, 0xf, 0xf, 0xff, 20, 16, 24},
47 {PERIPH_ID_SPI2, 0xf, 0xf, 0xff, 24, 0, 8},
48 {PERIPH_ID_SDMMC0, 0xf, 0xf, 0xff, 0, 0, 8},
49 {PERIPH_ID_SDMMC1, 0xf, 0xf, 0xff, 4, 16, 24},
50 {PERIPH_ID_SDMMC2, 0xf, 0xf, 0xff, 8, 0, 8},
51 {PERIPH_ID_SDMMC3, 0xf, 0xf, 0xff, 12, 16, 24},
52 {PERIPH_ID_I2S0, 0xf, 0xf, 0xff, 0, 0, 4},
53 {PERIPH_ID_I2S1, 0xf, 0xf, 0xff, 4, 12, 16},
54 {PERIPH_ID_SPI3, 0xf, 0xf, 0xff, 0, 0, 4},
55 {PERIPH_ID_SPI4, 0xf, 0xf, 0xff, 4, 12, 16},
56 {PERIPH_ID_SDMMC4, 0xf, 0xf, 0xff, 16, 0, 8},
57 {PERIPH_ID_PWM0, 0xf, 0xf, -1, 24, 0, -1},
58 {PERIPH_ID_PWM1, 0xf, 0xf, -1, 24, 0, -1},
59 {PERIPH_ID_PWM2, 0xf, 0xf, -1, 24, 0, -1},
60 {PERIPH_ID_PWM3, 0xf, 0xf, -1, 24, 0, -1},
61 {PERIPH_ID_PWM4, 0xf, 0xf, -1, 24, 0, -1},
68 {PERIPH_ID_UART0, 0xf, 0xf, -1, 4, 8, -1},
69 {PERIPH_ID_UART1, 0xf, 0xf, -1, 8, 12, -1},
70 {PERIPH_ID_UART2, 0xf, 0xf, -1, 12, 16, -1},
71 {PERIPH_ID_UART3, 0xf, 0xf, -1, 16, 20, -1},
72 {PERIPH_ID_I2C0, -1, 0x3f, -1, -1, 8, -1},
73 {PERIPH_ID_I2C1, -1, 0x3f, -1, -1, 8, -1},
74 {PERIPH_ID_I2C2, -1, 0x3f, -1, -1, 8, -1},
75 {PERIPH_ID_I2C3, -1, 0x3f, -1, -1, 8, -1},
76 {PERIPH_ID_I2C4, -1, 0x3f, -1, -1, 8, -1},
77 {PERIPH_ID_I2C5, -1, 0x3f, -1, -1, 8, -1},
78 {PERIPH_ID_I2C6, -1, 0x3f, -1, -1, 8, -1},
79 {PERIPH_ID_I2C7, -1, 0x3f, -1, -1, 8, -1},
80 {PERIPH_ID_SPI0, 0xf, 0xf, 0xff, 20, 20, 8},
81 {PERIPH_ID_SPI1, 0xf, 0xf, 0xff, 24, 24, 16},
82 {PERIPH_ID_SPI2, 0xf, 0xf, 0xff, 28, 28, 24},
83 {PERIPH_ID_SDMMC0, 0x7, 0x3ff, -1, 8, 0, -1},
84 {PERIPH_ID_SDMMC1, 0x7, 0x3ff, -1, 12, 10, -1},
85 {PERIPH_ID_SDMMC2, 0x7, 0x3ff, -1, 16, 20, -1},
86 {PERIPH_ID_I2C8, -1, 0x3f, -1, -1, 8, -1},
87 {PERIPH_ID_I2C9, -1, 0x3f, -1, -1, 8, -1},
88 {PERIPH_ID_I2S0, 0xf, 0xf, 0xff, 0, 0, 4},
89 {PERIPH_ID_I2S1, 0xf, 0xf, 0xff, 4, 12, 16},
90 {PERIPH_ID_SPI3, 0xf, 0xf, 0xff, 12, 16, 0},
91 {PERIPH_ID_SPI4, 0xf, 0xf, 0xff, 16, 20, 8},
92 {PERIPH_ID_PWM0, 0xf, 0xf, -1, 24, 28, -1},
93 {PERIPH_ID_PWM1, 0xf, 0xf, -1, 24, 28, -1},
94 {PERIPH_ID_PWM2, 0xf, 0xf, -1, 24, 28, -1},
95 {PERIPH_ID_PWM3, 0xf, 0xf, -1, 24, 28, -1},
96 {PERIPH_ID_PWM4, 0xf, 0xf, -1, 24, 28, -1},
97 {PERIPH_ID_I2C10, -1, 0x3f, -1, -1, 8, -1},
104 { 192000000, 0, 48, 3, 1, 0 },
105 { 180000000, 0, 45, 3, 1, 0 },
108 { 49152000, 0, 49, 3, 3, 9961 },
109 { 45158400, 0, 45, 3, 3, 10381 },
110 { 180633600, 0, 45, 3, 1, 10381 }
116 unsigned long m, p, s = 0, mask, fout; in exynos_get_pll_clk()
128 mask = 0x3ff; in exynos_get_pll_clk()
130 mask = 0x1ff; in exynos_get_pll_clk()
135 p = (r >> 8) & 0x3f; in exynos_get_pll_clk()
136 /* SDIV [2:0] */ in exynos_get_pll_clk()
137 s = r & 0x7; in exynos_get_pll_clk()
142 k = k & 0xffff; in exynos_get_pll_clk()
146 k = k & 0xfff; in exynos_get_pll_clk()
166 return 0; in exynos_get_pll_clk()
190 unsigned long r, k = 0; in exynos4_get_pll_clk()
209 return 0; in exynos4_get_pll_clk()
220 unsigned long r, k = 0; in exynos4x12_get_pll_clk()
239 return 0; in exynos4x12_get_pll_clk()
250 unsigned long r, k = 0, fout; in exynos5_get_pll_clk()
273 return 0; in exynos5_get_pll_clk()
297 if (fout_sel == 0) in exynos5_get_pll_clk()
309 unsigned long r, k = 0; in exynos542x_get_pll_clk()
338 return 0; in exynos542x_get_pll_clk()
354 for (i = 0; info[i].id != PERIPH_ID_NONE; i++) { in get_clk_bit_info()
368 unsigned long sclk = 0; in exynos5_get_periph_rate()
369 unsigned int src = 0, div = 0, sub_div = 0; in exynos5_get_periph_rate()
433 if (bit_info->src_bit >= 0) in exynos5_get_periph_rate()
448 return 0; in exynos5_get_periph_rate()
452 if (bit_info->div_bit >= 0) in exynos5_get_periph_rate()
456 if (bit_info->prediv_bit >= 0) in exynos5_get_periph_rate()
467 unsigned long sclk = 0; in exynos542x_get_periph_rate()
468 unsigned int src = 0, div = 0, sub_div = 0; in exynos542x_get_periph_rate()
524 if (bit_info->src_bit >= 0) in exynos542x_get_periph_rate()
542 return 0; in exynos542x_get_periph_rate()
546 if (bit_info->div_bit >= 0) in exynos542x_get_periph_rate()
550 if (bit_info->prediv_bit >= 0) in exynos542x_get_periph_rate()
565 return 0; in clock_get_periph_rate()
581 /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */ in exynos4_get_arm_clk()
582 core_ratio = (div >> 0) & 0x7; in exynos4_get_arm_clk()
583 core2_ratio = (div >> 28) & 0x7; in exynos4_get_arm_clk()
603 /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */ in exynos4x12_get_arm_clk()
604 core_ratio = (div >> 0) & 0x7; in exynos4x12_get_arm_clk()
605 core2_ratio = (div >> 28) & 0x7; in exynos4x12_get_arm_clk()
625 /* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */ in exynos5_get_arm_clk()
626 arm_ratio = (div >> 0) & 0x7; in exynos5_get_arm_clk()
627 arm2_ratio = (div >> 28) & 0x7; in exynos5_get_arm_clk()
644 if (s5p_get_cpu_rev() == 0) { in exynos4_get_pwm_clk()
650 sel = (sel >> 24) & 0xf; in exynos4_get_pwm_clk()
652 if (sel == 0x6) in exynos4_get_pwm_clk()
654 else if (sel == 0x7) in exynos4_get_pwm_clk()
656 else if (sel == 0x8) in exynos4_get_pwm_clk()
659 return 0; in exynos4_get_pwm_clk()
663 * PWM_RATIO [3:0] in exynos4_get_pwm_clk()
666 ratio = ratio & 0xf; in exynos4_get_pwm_clk()
671 return 0; in exynos4_get_pwm_clk()
703 * UART0_SEL [3:0] in exynos4_get_uart_clk()
711 sel = (sel >> (dev_index << 2)) & 0xf; in exynos4_get_uart_clk()
713 if (sel == 0x6) in exynos4_get_uart_clk()
715 else if (sel == 0x7) in exynos4_get_uart_clk()
717 else if (sel == 0x8) in exynos4_get_uart_clk()
720 return 0; in exynos4_get_uart_clk()
724 * UART0_RATIO [3:0] in exynos4_get_uart_clk()
732 ratio = (ratio >> (dev_index << 2)) & 0xf; in exynos4_get_uart_clk()
750 * UART0_SEL [3:0] in exynos4x12_get_uart_clk()
757 sel = (sel >> (dev_index << 2)) & 0xf; in exynos4x12_get_uart_clk()
759 if (sel == 0x6) in exynos4x12_get_uart_clk()
761 else if (sel == 0x7) in exynos4x12_get_uart_clk()
763 else if (sel == 0x8) in exynos4x12_get_uart_clk()
766 return 0; in exynos4x12_get_uart_clk()
770 * UART0_RATIO [3:0] in exynos4x12_get_uart_clk()
777 ratio = (ratio >> (dev_index << 2)) & 0xf; in exynos4x12_get_uart_clk()
790 int shift = 0; in exynos4_get_mmc_clk()
793 sel = (sel >> (dev_index << 2)) & 0xf; in exynos4_get_mmc_clk()
795 if (sel == 0x6) in exynos4_get_mmc_clk()
797 else if (sel == 0x7) in exynos4_get_mmc_clk()
799 else if (sel == 0x8) in exynos4_get_mmc_clk()
802 return 0; in exynos4_get_mmc_clk()
805 case 0: in exynos4_get_mmc_clk()
820 return 0; in exynos4_get_mmc_clk()
826 ratio = (ratio >> shift) & 0xf; in exynos4_get_mmc_clk()
827 pre_ratio = (pre_ratio >> (shift + 8)) & 0xff; in exynos4_get_mmc_clk()
846 * MMC4_RATIO [3:0] in exynos4_set_mmc_clk()
888 clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8), in exynos5_set_mmc_clk()
889 (div & 0xff) << ((dev_index << 4) + 8)); in exynos5_set_mmc_clk()
902 * MMC0_RATIO [9:0] in exynos5420_set_mmc_clk()
909 clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift); in exynos5420_set_mmc_clk()
923 * FIMD0_SEL [3:0] in exynos4_get_lcd_clk()
926 sel = sel & 0xf; in exynos4_get_lcd_clk()
929 * 0x6: SCLK_MPLL in exynos4_get_lcd_clk()
930 * 0x7: SCLK_EPLL in exynos4_get_lcd_clk()
931 * 0x8: SCLK_VPLL in exynos4_get_lcd_clk()
933 if (sel == 0x6) in exynos4_get_lcd_clk()
935 else if (sel == 0x7) in exynos4_get_lcd_clk()
937 else if (sel == 0x8) in exynos4_get_lcd_clk()
940 return 0; in exynos4_get_lcd_clk()
944 * FIMD0_RATIO [3:0] in exynos4_get_lcd_clk()
947 ratio = ratio & 0xf; in exynos4_get_lcd_clk()
965 * FIMD0_SEL [3:0] in exynos5_get_lcd_clk()
968 sel = sel & 0xf; in exynos5_get_lcd_clk()
971 * 0x6: SCLK_MPLL in exynos5_get_lcd_clk()
972 * 0x7: SCLK_EPLL in exynos5_get_lcd_clk()
973 * 0x8: SCLK_VPLL in exynos5_get_lcd_clk()
975 if (sel == 0x6) in exynos5_get_lcd_clk()
977 else if (sel == 0x7) in exynos5_get_lcd_clk()
979 else if (sel == 0x8) in exynos5_get_lcd_clk()
982 return 0; in exynos5_get_lcd_clk()
986 * FIMD0_RATIO [3:0] in exynos5_get_lcd_clk()
989 ratio = ratio & 0xf; in exynos5_get_lcd_clk()
1007 * 0: SCLK_RPLL in exynos5420_get_lcd_clk()
1020 * FIMD1_RATIO [3:0] in exynos5420_get_lcd_clk()
1023 ratio = ratio & 0xf; in exynos5420_get_lcd_clk()
1042 sel = (readl(&clk->src_disp10) >> 4) & 0x7; in exynos5800_get_lcd_clk()
1050 const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL, in exynos5800_get_lcd_clk()
1057 * FIMD1_RATIO [3:0] in exynos5800_get_lcd_clk()
1059 ratio = readl(&clk->div_disp10) & 0xf; in exynos5800_get_lcd_clk()
1071 * CLK_CAM [0] in exynos4_set_lcd_clk()
1083 * FIMD0_SEL [3:0] in exynos4_set_lcd_clk()
1087 * set lcd0 src clock 0x6: SCLK_MPLL in exynos4_set_lcd_clk()
1089 clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6); in exynos4_set_lcd_clk()
1093 * CLK_FIMD0 [0] in exynos4_set_lcd_clk()
1101 setbits_le32(&clk->gate_ip_lcd0, 1 << 0); in exynos4_set_lcd_clk()
1105 * FIMD0_RATIO [3:0] in exynos4_set_lcd_clk()
1113 clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1); in exynos4_set_lcd_clk()
1123 * CLK_CAM [0] in exynos5_set_lcd_clk()
1135 * FIMD0_SEL [3:0] in exynos5_set_lcd_clk()
1139 * set lcd0 src clock 0x6: SCLK_MPLL in exynos5_set_lcd_clk()
1141 clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6); in exynos5_set_lcd_clk()
1145 * CLK_FIMD0 [0] in exynos5_set_lcd_clk()
1153 setbits_le32(&clk->gate_ip_disp1, 1 << 0); in exynos5_set_lcd_clk()
1157 * FIMD0_RATIO [3:0] in exynos5_set_lcd_clk()
1165 clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0); in exynos5_set_lcd_clk()
1177 * 0: SCLK_RPLL in exynos5420_set_lcd_clk()
1181 cfg &= ~(0x1 << 4); in exynos5420_set_lcd_clk()
1182 cfg |= (0 << 4); in exynos5420_set_lcd_clk()
1187 * FIMD1_RATIO [3:0] in exynos5420_set_lcd_clk()
1190 cfg &= ~(0xf << 0); in exynos5420_set_lcd_clk()
1191 cfg |= (0 << 0); in exynos5420_set_lcd_clk()
1207 cfg = readl(&clk->src_disp10) | (0x7 << 4); in exynos5800_set_lcd_clk()
1212 * FIMD1_RATIO [3:0] in exynos5800_set_lcd_clk()
1214 clrsetbits_le32(&clk->div_disp10, 0xf << 0, 0x0 << 0); in exynos5800_set_lcd_clk()
1224 * FIMD0_SEL [3:0] in exynos4_set_mipi_clk()
1228 * set mipi0 src clock 0x6: SCLK_MPLL in exynos4_set_mipi_clk()
1230 clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12); in exynos4_set_mipi_clk()
1234 * FIMD0_MASK [0] in exynos4_set_mipi_clk()
1238 * set src mask mipi0 0x1: Unmask in exynos4_set_mipi_clk()
1240 setbits_le32(&clk->src_mask_lcd0, 0x1 << 12); in exynos4_set_mipi_clk()
1244 * CLK_FIMD0 [0] in exynos4_set_mipi_clk()
1256 * FIMD0_RATIO [3:0] in exynos4_set_mipi_clk()
1264 clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16); in exynos4_set_mipi_clk()
1283 for (i = 0; i < ARRAY_SIZE(exynos5_epll_div); i++) { in exynos5_set_epll_clk()
1291 epll_con_k = exynos5_epll_div[i].k_dsm << 0; in exynos5_set_epll_clk()
1309 start = get_timer(0); in exynos5_set_epll_clk()
1312 (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) { in exynos5_set_epll_clk()
1318 return 0; in exynos5_set_epll_clk()
1327 if (i2s_id == 0) { in exynos5_set_i2s_clk_source()
1338 return 0; in exynos5_set_i2s_clk_source()
1349 if ((dst_frq == 0) || (src_frq == 0)) { in exynos5_set_i2s_clk_prescaler()
1356 if (i2s_id == 0) { in exynos5_set_i2s_clk_prescaler()
1377 return 0; in exynos5_set_i2s_clk_prescaler()
1386 * @param main_scalar_bits Number of main scalar bits, must be > 0 and < 32
1387 * @param fine_scalar_bits Number of fine scalar bits, must be > 0 and < 32
1413 if (input_rate == 0 || target_rate == 0) in clock_calc_best_scalar()
1429 if (error >= 0 && error <= best_error) { in clock_calc_best_scalar()
1447 unsigned mask = 0xff; in exynos5_set_spi_clk()
1451 if (main < 0) { in exynos5_set_spi_clk()
1462 shift = 0; in exynos5_set_spi_clk()
1472 shift = 0; in exynos5_set_spi_clk()
1477 shift = 0; in exynos5_set_spi_clk()
1493 return 0; in exynos5_set_spi_clk()
1504 unsigned div_mask = 0xf, pre_div_mask = 0xff; in exynos5420_set_spi_clk()
1509 if (main < 0) { in exynos5420_set_spi_clk()
1540 pre_shift = 0; in exynos5420_set_spi_clk()
1558 return 0; in exynos5420_set_spi_clk()
1571 ratio &= 0xf; in exynos4_get_i2c_clk()
1588 return 0; in get_pll_clk()
1601 return 0; in get_arm_clk()
1611 return 0; in get_i2c_clk()
1624 return 0; in get_pwm_clk()
1632 case 0: in get_uart_clk()
1657 return 0; in get_uart_clk()
1668 case 0: in get_mmc_clk()
1691 if (div > 0) in set_mmc_clk()
1717 return 0; in get_lcd_clk()
1748 return 0; in set_spi_clk()
1757 return 0; in set_i2s_clk_prescaler()
1765 return 0; in set_i2s_clk_source()
1773 return 0; in set_epll_clk()