Lines Matching refs:r7
51 ldr r7, [r6]
52 and r7, r7, r8
53 str r7, [r6]
57 ldr r7, [r6]
58 orr r7, r7, $0x02
59 str r7, [r6]
64 ldr r7, [r6]
65 ands r7, r7, $0x02
71 ldr r7, [r6]
72 ands r7, r7, $0x100
103 ldr r7, PLL_CLKSRC_MASK
105 and r8, r8, r7
111 ldr r7, PLL_ENSRC_MASK
112 and r8, r8, r7
116 ldr r7, PLL_BYPASS_MASK
117 and r8, r8, r7
127 ldr r7, PLL_RESET_MASK
128 and r8, r8, r7
132 ldr r7, PLL_PWRUP_MASK
133 and r8, r8, r7
137 ldr r7, PLL_DISABLE_ENABLE_MASK
138 and r8, r8, r7
168 ldr r7, [r6]
169 orr r7, r7, $0x01
170 str r7, [r6]
175 ldr r7, [r6]
176 ands r7, r7, $0x01
191 ldr r7, [r6]
192 orr r7, r7, $0x01
193 str r7, [r6]
198 ldr r7, [r6]
199 ands r7, r7, $0x01
233 ldr r7, [r6]
234 and r7, r7, r8
235 orr r7, r7, $0x03
236 str r7, [r6]
240 ldr r7, [r6]
241 orr r7, r7, $0x01
242 str r7, [r6]
247 ldr r7, [r6]
248 ands r7, r7, $0x01
254 ldr r7, [r6]
255 and r7, r7, $MDSTAT_STATE
256 cmp r7, $0x03
265 ldr r7, DDRCTL_VAL
266 str r7, [r6]
270 ldr r7, SDCFG_VAL
271 str r7, [r6]
275 ldr r7, SDTIM0_VAL_162MHz
276 str r7, [r6]
280 ldr r7, SDTIM1_VAL_162MHz
281 str r7, [r6]
292 ldr r7, SDREF_VAL
293 str r7, [r6]
301 ldr r7, DUMMY_VAL
302 str r7, [r8]
303 ldr r7, [r8]
308 ldr r7, [r6]
309 and r7, r7, r8
310 orr r7, r7, $0x01
311 str r7, [r6]
315 ldr r7, [r6]
316 orr r7, r7, $0x01
317 str r7, [r6]
322 ldr r7, [r6]
323 ands r7, r7, $0x01
329 ldr r7, [r6]
330 and r7, r7, $MDSTAT_STATE
331 cmp r7, $0x01
340 ldr r7, [r6]
341 orr r7, r7, $0x03
342 str r7, [r6]
346 ldr r7, [r6]
347 orr r7, r7, $0x01
348 str r7, [r6]
353 ldr r7, [r6]
354 ands r7, r7, $0x01
360 ldr r7, [r6]
361 and r7, r7, $MDSTAT_STATE
362 cmp r7, $0x03
377 ldr r7, PLL_CLKSRC_MASK
379 and r8, r8, r7
385 ldr r7, PLL_ENSRC_MASK
386 and r8, r8, r7
390 ldr r7, PLL_BYPASS_MASK
391 and r8, r8, r7
402 ldr r7, PLL_RESET_MASK
403 and r8, r8, r7
411 ldr r7, PLL_PWRUP_MASK
412 and r8, r8, r7
416 ldr r7, PLL_DISABLE_ENABLE_MASK
417 and r8, r8, r7
506 ldr r7, [r6]
507 mov r8, r7, LSL #32-10
509 ldr r7, VTP_RECAL
510 orr r8, r7, r8
511 ldr r7, VTP_EN
512 orr r8, r7, r8