Lines Matching refs:r6

50 	ldr	r6, MDCTL_GEM
51 	ldr	r7, [r6]
53 	str	r7, [r6]
56 	ldr	r6, PTCMD
57 	ldr	r7, [r6]
59 	str	r7, [r6]
63 	ldr	r6, PTSTAT
64 	ldr	r7, [r6]
70 	ldr	r6, MDSTAT_GEM
71 	ldr	r7, [r6]
77 	ldr	r6, P1394
79 	str	r10, [r6]
84 	ldr	r6, DFT_ENABLE
86 	str	r10, [r6]
88 	ldr	r6, MMARG_BRF0
90 	str	r10, [r6]
92 	ldr	r6, DFT_ENABLE
94 	str	r10, [r6]
102 	ldr	r6, PLL2_CTL
104 	ldr	r8, [r6]
108 	str	r8, [r6]
113 	str	r8, [r6]
118 	str	r8, [r6]
129 	str	r8, [r6]
134 	str	r8, [r6]
139 	str	r8, [r6]
142 	ldr	r6, PLL2_PLLM
144 	str	r2, [r6]
147 	ldr	r6, PLL2_DIV2
149 	str	r3, [r6]
152 	ldr	r6, PLL2_DIV1
154 	str	r4, [r6]
158 	ldr	r6, PLL2_DIV2
159 	ldr	r9, [r6]
164 	str	r8, [r6]
167 	ldr	r6, PLL2_PLLCMD
168 	ldr	r7, [r6]
170 	str	r7, [r6]
173 	ldr	r6, PLL2_PLLSTAT
175 	ldr	r7, [r6]
181 	ldr	r6, PLL2_DIV1
182 	ldr	r9, [r6]
187 	str	r8, [r6]
190 	ldr	r6, PLL2_PLLCMD
191 	ldr	r7, [r6]
193 	str	r7, [r6]
196 	ldr	r6, PLL2_PLLSTAT
198 	ldr	r7, [r6]
209 	ldr	r6, PLL2_CTL
210 	ldr	r8, [r6]
212 	str	r8, [r6]
221 	ldr	r6, PLL2_CTL
222 	ldr	r8, [r6]
224 	str	r8, [r6]
232 	ldr	r6, MDCTL_DDR2
233 	ldr	r7, [r6]
236 	str	r7, [r6]
239 	ldr	r6, PTCMD
240 	ldr	r7, [r6]
242 	str	r7, [r6]
246 	ldr	r6, PTSTAT
247 	ldr	r7, [r6]
253 	ldr	r6, MDSTAT_DDR2
254 	ldr	r7, [r6]
264 	ldr	r6, DDRCTL
266 	str	r7, [r6]
269 	ldr	r6, SDCFG
271 	str	r7, [r6]
274 	ldr	r6, SDTIM0
276 	str	r7, [r6]
279 	ldr	r6, SDTIM1
281 	str	r7, [r6]
291 	ldr	r6, SDREF
293 	str	r7, [r6]
307 	ldr	r6, MDCTL_DDR2
308 	ldr	r7, [r6]
311 	str	r7, [r6]
314 	ldr	r6, PTCMD
315 	ldr	r7, [r6]
317 	str	r7, [r6]
321 	ldr	r6, PTSTAT
322 	ldr	r7, [r6]
328 	ldr	r6, MDSTAT_DDR2
329 	ldr	r7, [r6]
339 	ldr	r6, MDCTL_DDR2
340 	ldr	r7, [r6]
342 	str	r7, [r6]
345 	ldr	r6, PTCMD
346 	ldr	r7, [r6]
348 	str	r7, [r6]
352 	ldr	r6, PTSTAT
353 	ldr	r7, [r6]
359 	ldr	r6, MDSTAT_DDR2
360 	ldr	r7, [r6]
366 	ldr	r6, CFGTEST
368 	str	r3, [r6]
376 	ldr	r6, PLL1_CTL
378 	ldr	r8, [r6]
382 	str	r8, [r6]
387 	str	r8, [r6]
392 	str	r8, [r6]
404 	str	r8, [r6]
408 	str	r8, [r6]
413 	str	r8, [r6]
418 	str	r8, [r6]
421 	ldr	r6, PLL1_PLLM
423 	str	r3, [r6]
433 	ldr	r6, PLL1_CTL
435 	str	r8, [r6]
446 	str	r8, [r6]
501 	ldr	r6, DFT_ENABLE
503 	str	r10, [r6]
505 	ldr	r6, DDRVTPR
506 	ldr	r7, [r6]
527 	ldr	r6, DFT_ENABLE
529 	str	r10, [r6]