Lines Matching refs:ldr
39 ldr r0, =EINT_ENABLE0
41 ldr r0, =EINT_ENABLE1
49 ldr r8, PSC_GEM_FLAG_CLEAR
50 ldr r6, MDCTL_GEM
51 ldr r7, [r6]
56 ldr r6, PTCMD
57 ldr r7, [r6]
63 ldr r6, PTSTAT
64 ldr r7, [r6]
70 ldr r6, MDSTAT_GEM
71 ldr r7, [r6]
77 ldr r6, P1394
84 ldr r6, DFT_ENABLE
88 ldr r6, MMARG_BRF0
89 ldr r10, MMARG_BRF0_VAL
92 ldr r6, DFT_ENABLE
102 ldr r6, PLL2_CTL
103 ldr r7, PLL_CLKSRC_MASK
104 ldr r8, [r6]
111 ldr r7, PLL_ENSRC_MASK
116 ldr r7, PLL_BYPASS_MASK
127 ldr r7, PLL_RESET_MASK
132 ldr r7, PLL_PWRUP_MASK
137 ldr r7, PLL_DISABLE_ENABLE_MASK
142 ldr r6, PLL2_PLLM
147 ldr r6, PLL2_DIV2
152 ldr r6, PLL2_DIV1
157 ldr r8, PLL2_DIV_MASK
158 ldr r6, PLL2_DIV2
159 ldr r9, [r6]
167 ldr r6, PLL2_PLLCMD
168 ldr r7, [r6]
173 ldr r6, PLL2_PLLSTAT
175 ldr r7, [r6]
180 ldr r8, PLL2_DIV_MASK
181 ldr r6, PLL2_DIV1
182 ldr r9, [r6]
190 ldr r6, PLL2_PLLCMD
191 ldr r7, [r6]
196 ldr r6, PLL2_PLLSTAT
198 ldr r7, [r6]
209 ldr r6, PLL2_CTL
210 ldr r8, [r6]
215 ldr r10, PLL_LOCK_COUNT
221 ldr r6, PLL2_CTL
222 ldr r8, [r6]
231 ldr r8, PSC_FLAG_CLEAR
232 ldr r6, MDCTL_DDR2
233 ldr r7, [r6]
239 ldr r6, PTCMD
240 ldr r7, [r6]
246 ldr r6, PTSTAT
247 ldr r7, [r6]
253 ldr r6, MDSTAT_DDR2
254 ldr r7, [r6]
264 ldr r6, DDRCTL
265 ldr r7, DDRCTL_VAL
269 ldr r6, SDCFG
270 ldr r7, SDCFG_VAL
274 ldr r6, SDTIM0
275 ldr r7, SDTIM0_VAL_162MHz
279 ldr r6, SDTIM1
280 ldr r7, SDTIM1_VAL_162MHz
284 ldr r10, MASK_VAL
285 ldr r8, SDCFG
286 ldr r9, SDCFG_VAL
291 ldr r6, SDREF
292 ldr r7, SDREF_VAL
300 ldr r8, DDR2_START_ADDR
301 ldr r7, DUMMY_VAL
303 ldr r7, [r8]
306 ldr r8, PSC_FLAG_CLEAR
307 ldr r6, MDCTL_DDR2
308 ldr r7, [r6]
314 ldr r6, PTCMD
315 ldr r7, [r6]
321 ldr r6, PTSTAT
322 ldr r7, [r6]
328 ldr r6, MDSTAT_DDR2
329 ldr r7, [r6]
339 ldr r6, MDCTL_DDR2
340 ldr r7, [r6]
345 ldr r6, PTCMD
346 ldr r7, [r6]
352 ldr r6, PTSTAT
353 ldr r7, [r6]
359 ldr r6, MDSTAT_DDR2
360 ldr r7, [r6]
366 ldr r6, CFGTEST
376 ldr r6, PLL1_CTL
377 ldr r7, PLL_CLKSRC_MASK
378 ldr r8, [r6]
385 ldr r7, PLL_ENSRC_MASK
390 ldr r7, PLL_BYPASS_MASK
402 ldr r7, PLL_RESET_MASK
411 ldr r7, PLL_PWRUP_MASK
416 ldr r7, PLL_DISABLE_ENABLE_MASK
421 ldr r6, PLL1_PLLM
433 ldr r6, PLL1_CTL
438 ldr r10, PLL_LOCK_COUNT
456 ldr r0, _PINMUX0
457 ldr r1, _DEV_SETTING
460 ldr r0, WAITCFG
461 ldr r1, WAITCFG_VAL
462 ldr r2, [r0]
466 ldr r0, ACFG3
467 ldr r1, ACFG3_VAL
468 ldr r2, [r0]
472 ldr r0, ACFG4
473 ldr r1, ACFG4_VAL
474 ldr r2, [r0]
478 ldr r0, ACFG5
479 ldr r1, ACFG5_VAL
480 ldr r2, [r0]
487 ldr r0, VTPIOCR
488 ldr r1, VTP_MMR0
491 ldr r0, VTPIOCR
492 ldr r1, VTP_MMR1
496 ldr r10, VTP_LOCK_COUNT
501 ldr r6, DFT_ENABLE
505 ldr r6, DDRVTPR
506 ldr r7, [r6]
509 ldr r7, VTP_RECAL
511 ldr r7, VTP_EN
517 ldr r10, VTP_LOCK_COUNT
522 ldr r1, [r0]
523 ldr r2, VTP_MASK
527 ldr r6, DFT_ENABLE