Lines Matching full:word

541 	.word	0x01c40000		/* Device Configuration Registers */
543 	.word	0x01c40004		/* Device Configuration Registers */
546 	.word	0x00000c1f
549 	.word	0x01e00004
551 	.word	0
553 	.word	0x01e00014
555 	.word	0x3ffffffd
557 	.word	0x01e00018
559 	.word	0x3ffffffd
561 	.word	0x01e0001c
563 	.word	0x3ffffffd
566 	.word	0x01c41a34
568 	.word	0x01c41834
571 	.word	0x01c41120
573 	.word	0x01c41128
576 	.word	0x01c48018
578 	.word	0x01c4801c
581 	.word	0xffffffe0
583 	.word	0xfffffeff
587 	.word	0x200000e4
589 	.word	0x50006405
591 	.word	0x2000000c
593 	.word	0x000005c3
595 	.word	0x20000008
598 	.word	0x00178622
600 	.word	0x00178632
605 	.word	0x20000010
607 	.word	0x28923211
609 	.word	0x20000014
611 	.word	0x0016c722
613 	.word	0x200000f0	/* VTP IO Control register */
615 	.word	0x01c42030	/* DDR VPTR MMR */
617 	.word	0x201f
619 	.word	0xa01f
621 	.word	0x01c4004c
623 	.word	0x5b0
625 	.word	0xffffdfff
627 	.word	0x08000
629 	.word	0x02000
631 	.word	0x80010000
633 	.word	0x00000fff
637 	.word	0x01c41a9c
639 	.word	0x01c4189c
643 	.word	0x01c41a20
646 	.word	0xfffffeff	/* Mask the Clock Mode bit */
648 	.word	0xffffffdf	/* Select the PLLEN source */
650 	.word	0xfffffffe	/* Put the PLL in BYPASS */
652 	.word	0xfffffff7	/* Put the PLL in Reset Mode */
654 	.word	0xfffffffd	/* PLL Power up Mask Bit  */
656 	.word	0xffffffef	/* Enable the PLL from Disable */
658 	.word	0x2000
662 	.word	0x01c40900
664 	.word	0x01c40910
668 	.word	0x01c40d00
670 	.word	0x01c40d10
672 	.word	0x01c40d18
674 	.word	0x01c40d1c
676 	.word	0x01c40d38
678 	.word	0x01c40d3c
680 	.word	0xffff7fff
683 	.word	0x01c42010	/* BRF margin mode 0 (R/W)*/
685 	.word	0x00444400
688 	.word	0x80000000
690 	.word	0xa55aa55a