116 static unsigned pll_div(volatile void *pllbase, unsigned offset)  in pll_div()  argument
120 	div = REG(pllbase + offset);  in pll_div()
124 static inline unsigned pll_prediv(volatile void *pllbase)  in pll_prediv()  argument
128 	if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)  in pll_prediv()
131 		return pll_div(pllbase, PLLC_PREDIV);  in pll_prediv()
133 	return pll_div(pllbase, PLLC_PREDIV);  in pll_prediv()
138 static inline unsigned pll_postdiv(volatile void *pllbase)  in pll_postdiv()  argument
141 	return pll_div(pllbase, PLLC_POSTDIV);  in pll_postdiv()
143 	if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)  in pll_postdiv()
144 		return pll_div(pllbase, PLLC_POSTDIV);  in pll_postdiv()
151 	volatile void	*pllbase = (volatile void *) pll_addr;  in pll_sysclk_mhz()  local
159 	if (readl(pllbase + PLLC_PLLCTL) & BIT(0)) {  in pll_sysclk_mhz()
160 		base /= pll_prediv(pllbase);  in pll_sysclk_mhz()
162 		base *=  2 * (readl(pllbase + PLLC_PLLM) & 0x0ff);  in pll_sysclk_mhz()
164 		base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff);  in pll_sysclk_mhz()
166 		base /= pll_postdiv(pllbase);  in pll_sysclk_mhz()
168 	return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));  in pll_sysclk_mhz()
187 	unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE;  in set_cpu_clk_info()  local
189 	pllbase = DAVINCI_PLL_CNTRL1_BASE;  in set_cpu_clk_info()
191 	gd->bd->bi_arm_freq = pll_sysclk_mhz(pllbase, ARM_PLLDIV);  in set_cpu_clk_info()
200 	pllbase = DAVINCI_PLL_CNTRL1_BASE;  in set_cpu_clk_info()
202 	pllbase = DAVINCI_PLL_CNTRL0_BASE;  in set_cpu_clk_info()
204 	gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2;  in set_cpu_clk_info()