Lines Matching refs:x10
83 mrs x10, mpidr_el1
84 lsr x9, x10, #32
85 bfi x10, x9, #24, #8 /* w10 is aff3:aff2:aff1:aff0 */
104 add x10, x9, #(1 << 16) /* SGI_Base */
106 str w11, [x10, GICR_IGROUPRn]
107 str wzr, [x10, GICR_IGROUPMODRn] /* SGIs|PPIs Group1NS */
109 str w11, [x10, GICR_ISENABLERn]
117 mrs x10, ICC_SRE_EL3
118 orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */
120 msr ICC_SRE_EL3, x10
124 mrs x10, ICC_SRE_EL2
125 orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */
127 msr ICC_SRE_EL2, x10
136 mov x10, #0x3 /* EnableGrp1NS | EnableGrp1S */
137 msr ICC_IGRPEN1_EL3, x10
144 mov x10, #0x3 /* EnableGrp1NS | EnableGrp1S */
145 msr ICC_IGRPEN1_EL1, x10
151 mov x10, #0xf0 /* Non-Secure access to ICC_PMR_EL1 */
152 msr ICC_PMR_EL1, x10
156 mrs x10, ICC_SRE_EL3
157 orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */
159 msr ICC_SRE_EL3, x10
162 mrs x10, ICC_SRE_EL2
163 orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */
165 msr ICC_SRE_EL2, x10
168 mov x10, #0x3 /* EnableGrp1NS | EnableGrp1S */
169 msr ICC_IGRPEN1_EL3, x10
178 mov x10, #0x1 << 7 /* Non-Secure access to ICC_PMR_EL1 */
179 msr ICC_PMR_EL1, x10