arm/lib/gic_64.S

30 	mov	w9, #0x37		/* EnableGrp0 | EnableGrp1NS */
34 	and	w10, w9, #0x1f		/* ITLinesNumber */
38 	mov	w9, #~0
39 0:	str	w9, [x11], #0x4
40 	str	wzr, [x12], #0x4	/* Config SPIs as Group1NS */
41 	sub	w10, w10, #0x1
42 	cbnz	w10, 0b
44 	mov	w9, #0x3		/* EnableGrp0 | EnableGrp1 */
47 	and	w10, w9, #0x1f		/* ITLinesNumber */
50 	mov	w9, #~0			/* Config SPIs as Grp1 */
51 	str	w9, [x11], #0x4
52 0:	str	w9, [x11], #0x4
53 	sub	w10, w10, #0x1
54 	cbnz	w10, 0b
84 	lsr	x9, x10, #32
85 	bfi	x10, x9, #24, #8	/* w10 is aff3:aff2:aff1:aff0 */
86 	mov	x9, x0
87 1:	ldr	x11, [x9, GICR_TYPER]
91 	add	x9, x9, #(2 << 16)
94 	/* x9: ReDistributor Base Address of Current CPU */
95 2:	mov	w10, #~0x2
96 	ldr	w11, [x9, GICR_WAKER]
98 	str	w11, [x9, GICR_WAKER]
101 3:	ldr	w10, [x9, GICR_WAKER]
104 	add	x10, x9, #(1 << 16)	/* SGI_Base */
105 	mov	w11, #~0
108 	mov	w11, #0x1		/* Enable SGI 0 */
118 	orr	x10, x10, #0xf		/* SRE & Disable IRQ/FIQ Bypass & */
125 	orr	x10, x10, #0xf		/* SRE & Disable IRQ/FIQ Bypass & */
132 	cmp	x0, 0xC
136 	mov	x10, #0x3		/* EnableGrp1NS | EnableGrp1S */
144 	mov	x10, #0x3		/* EnableGrp1NS | EnableGrp1S */
151 	mov	x10, #0xf0		/* Non-Secure access to ICC_PMR_EL1 */
157 	orr	x10, x10, #0xf		/* SRE & Disable IRQ/FIQ Bypass & */
163 	orr	x10, x10, #0xf		/* SRE & Disable IRQ/FIQ Bypass & */
168 	mov	x10, #0x3		/* EnableGrp1NS | EnableGrp1S */
178 	mov	x10, #0x1 << 7		/* Non-Secure access to ICC_PMR_EL1 */
189 	mov	w9, #~0			/* Config SGIs and PPIs as Grp1 */
191 	mov	w9, #0x1		/* Enable SGI 0 */
195 	mov	w9, #0x1e7		/* Disable IRQ/FIQ Bypass & */
200 	mov	w9, #0x1 << 7		/* Non-Secure access to GICC_PMR */
216 	mov	x9, #(1 << 40)
217 	msr	ICC_ASGI1R_EL1, x9
220 	mov	w9, #0x8000
221 	movk	w9, #0x100, lsl #16
234  * Wait for SGI 0 from master.
239 	gic_wait_for_interrupt_m x9