Lines Matching +full:0 +full:x54000000
680 /* Initialize general purpose I2C(0) on the SoC */
689 #define OMAP_ABB_NOMINAL_OPP 0
692 #define OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK (0x1 << 0)
693 #define OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK (0x1 << 1)
694 #define OMAP_ABB_CONTROL_OPP_CHANGE_MASK (0x1 << 2)
695 #define OMAP_ABB_CONTROL_SR2_IN_TRANSITION_MASK (0x1 << 6)
696 #define OMAP_ABB_SETUP_SR2EN_MASK (0x1 << 0)
697 #define OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK (0x1 << 2)
698 #define OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK (0x1 << 1)
699 #define OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK (0xff << 8)
707 #define OMAP44xx 0x44000000
712 return (*omap_si_rev & 0xFF000000) == OMAP44xx; in is_omap44xx()
715 #define OMAP54xx 0x54000000
720 return ((*omap_si_rev & 0xFF000000) == OMAP54xx); in is_omap54xx()
723 #define DRA7XX 0x07000000
724 #define DRA72X 0x07200000
729 return ((*omap_si_rev & 0xFF000000) == DRA7XX); in is_dra7xx()
735 return (*omap_si_rev & 0xFFF00000) == DRA72X; in is_dra72x()
746 #define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF
747 #define OMAP4430_ES1_0 0x44300100
748 #define OMAP4430_ES2_0 0x44300200
749 #define OMAP4430_ES2_1 0x44300210
750 #define OMAP4430_ES2_2 0x44300220
751 #define OMAP4430_ES2_3 0x44300230
752 #define OMAP4460_ES1_0 0x44600100
753 #define OMAP4460_ES1_1 0x44600110
754 #define OMAP4470_ES1_0 0x44700100
757 #define OMAP5430_SILICON_ID_INVALID 0
758 #define OMAP5430_ES1_0 0x54300100
759 #define OMAP5432_ES1_0 0x54320100
760 #define OMAP5430_ES2_0 0x54300200
761 #define OMAP5432_ES2_0 0x54320200
764 #define DRA752_ES1_0 0x07520100
765 #define DRA752_ES1_1 0x07520110
766 #define DRA752_ES2_0 0x07520200
767 #define DRA722_ES1_0 0x07220100
768 #define DRA722_ES2_0 0x07220200
774 #define TST_DEVICE 0x0
775 #define EMU_DEVICE 0x1
776 #define HS_DEVICE 0x2
777 #define GP_DEVICE 0x3
784 #define OMAP_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
785 #define OMAP_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
786 #define OMAP_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
787 #define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
788 #define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
789 #define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
790 #define OMAP_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
791 #define OMAP_SRAM_SCRATCH_BOOT_PARAMS (SRAM_SCRATCH_SPACE_ADDR + 0x24)
793 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR + 0x28)
794 #define TI_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200)
799 #define DEVICE_DATA_OFFSET 0x18
800 #define BOOT_MODE_OFFSET 0x8
802 #define CH_FLAGS_CHSETTINGS (1 << 0)