Lines Matching full:rcc
41 u32 cr; /* RCC clock control */
42 u32 pllcfgr; /* RCC PLL configuration */
43 u32 cfgr; /* RCC clock configuration */
44 u32 cir; /* RCC clock interrupt */
45 u32 ahb1rstr; /* RCC AHB1 peripheral reset */
46 u32 ahb2rstr; /* RCC AHB2 peripheral reset */
47 u32 ahb3rstr; /* RCC AHB3 peripheral reset */
49 u32 apb1rstr; /* RCC APB1 peripheral reset */
50 u32 apb2rstr; /* RCC APB2 peripheral reset */
52 u32 ahb1enr; /* RCC AHB1 peripheral clock enable */
53 u32 ahb2enr; /* RCC AHB2 peripheral clock enable */
54 u32 ahb3enr; /* RCC AHB3 peripheral clock enable */
56 u32 apb1enr; /* RCC APB1 peripheral clock enable */
57 u32 apb2enr; /* RCC APB2 peripheral clock enable */
59 u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */
60 u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */
61 u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */
63 u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */
64 u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */
66 u32 bdcr; /* RCC Backup domain control */
67 u32 csr; /* RCC clock control & status */
69 u32 sscgr; /* RCC spread spectrum clock generation */
70 u32 plli2scfgr; /* RCC PLLI2S configuration */