Lines Matching +full:0 +full:x32000
24 #define OMAP54XX_L4_CORE_BASE 0x4A000000
25 #define OMAP54XX_L4_WKUP_BASE 0x4Ae00000
26 #define OMAP54XX_L4_PER_BASE 0x48000000
29 #define CONTROL_CORE_ID_CODE 0x4A002204
30 #define CONTROL_WKUP_ID_CODE 0x4AE0C204
39 #define DRA7_USB_OTG_SS1_BASE 0x48890000
40 #define DRA7_USB_OTG_SS1_GLUE_BASE 0x48880000
41 #define DRA7_USB3_PHY1_PLL_CTRL 0x4A084C00
42 #define DRA7_USB3_PHY1_POWER 0x4A002370
43 #define DRA7_USB2_PHY1_POWER 0x4A002300
45 #define DRA7_USB_OTG_SS2_BASE 0x488D0000
46 #define DRA7_USB_OTG_SS2_GLUE_BASE 0x488C0000
47 #define DRA7_USB2_PHY2_POWER 0x4A002E74
49 #define OMAP5XX_USB_OTG_SS_BASE 0x4A030000
50 #define OMAP5XX_USB_OTG_SS_GLUE_BASE 0x4A020000
51 #define OMAP5XX_USB3_PHY_PLL_CTRL 0x4A084C00
52 #define OMAP5XX_USB3_PHY_POWER 0x4A002370
53 #define OMAP5XX_USB2_PHY_POWER 0x4A002300
57 #define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F
58 #define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F
59 #define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F
60 #define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F
61 #define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F
62 #define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F
63 #define DRA752_CONTROL_ID_CODE_ES2_0 0x2B99002F
64 #define DRA722_CONTROL_ID_CODE_ES1_0 0x0B9BC02F
65 #define DRA722_CONTROL_ID_CODE_ES2_0 0x1B9BC02F
68 #define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000)
69 #define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000)
70 #define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000)
71 #define UART4_BASE (OMAP54XX_L4_PER_BASE + 0x6e000)
74 #define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000)
75 #define GPT2_BASE (OMAP54XX_L4_PER_BASE + 0x32000)
76 #define GPT3_BASE (OMAP54XX_L4_PER_BASE + 0x34000)
79 #define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000)
82 #define QSPI_BASE 0x4B300000
85 #define DWC_AHSATA_BASE 0x4A140000
92 #define WD_UNLOCK1 0xAAAA
93 #define WD_UNLOCK2 0x5555
96 #define TCLR_ST (0x1 << 0)
97 #define TCLR_AR (0x1 << 1)
98 #define TCLR_PRE (0x1 << 5)
101 #define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5)
102 #define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f
103 #define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110
104 #define CONTROL_EFUSE_2_OVERRIDE 0x00084000
107 #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C
108 #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E
109 #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C
111 #define CONTROL_LPDDR2IO_3_VAL 0xA0888C00
114 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
124 unsigned char res[0x10];
125 unsigned int s32k_cr; /* 0x10 */
128 #define DEVICE_TYPE_SHIFT 0x6
129 #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
132 #define ds_120_ohm 0x0
133 #define ds_60_ohm 0x1
134 #define ds_45_ohm 0x2
135 #define ds_30_ohm 0x3
136 #define ds_mask 0x3
139 #define sc_slow 0x0
140 #define sc_medium 0x1
141 #define sc_fast 0x2
142 #define sc_na 0x3
143 #define sc_mask 0x3
146 #define lb_5_12_pf 0x0
147 #define lb_12_25_pf 0x1
148 #define lb_25_50_pf 0x2
149 #define lb_50_80_pf 0x3
150 #define lb_mask 0x3
152 #define usb_i_mask 0x7
154 #define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN 0x80828082
155 #define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200
156 #define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421
157 #define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084
158 #define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000
160 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL 0x7C7C7C6C
161 #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL 0x64646464
162 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE 0xBAE8C631
163 #define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC
164 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0
166 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C
167 #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64646464
168 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631
169 #define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xBC6318DC
170 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000
172 #define EFUSE_1 0x45145100
173 #define EFUSE_2 0x45145100
174 #define EFUSE_3 0x45145100
175 #define EFUSE_4 0x45145100
188 #define NON_SECURE_SRAM_START 0x40300000
189 #define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */
190 #define NON_SECURE_SRAM_IMG_END 0x4037C000
192 #define NON_SECURE_SRAM_START 0x40300000
193 #define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */
194 #define NON_SECURE_SRAM_IMG_END 0x4031E000
199 #define SRAM_ROM_VECT_BASE 0x4031F000
205 #define SRCODE_READ_XS_MASK (0xff << 12)
209 #define DIVIDE_FACTOR_XS_MASK (0x7f << 4)
211 #define MULTIPLY_FACTOR_XS_MASK (0x7 << 1)
212 #define SRCODE_OVERRIDE_SEL_XS_SHIFT 0
213 #define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0)
220 #define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7)
221 #define OMAP_ABB_MM_TXDONE_MASK (0x1 << 31)
222 #define OMAP_ABB_IVA_TXDONE_MASK (0x1 << 30)
223 #define OMAP_ABB_EVE_TXDONE_MASK (0x1 << 29)
224 #define OMAP_ABB_GPU_TXDONE_MASK (0x1 << 28)
227 #define OMAP5_PROD_ABB_FUSE_VSET_MASK (0x1F << 20)
228 #define OMAP5_PROD_ABB_FUSE_ENABLE_MASK (0x1 << 25)
229 #define DRA7_ABB_FUSE_VSET_MASK (0x1F << 20)
230 #define DRA7_ABB_FUSE_ENABLE_MASK (0x1 << 25)
231 #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10)
232 #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0)