Lines Matching +full:0 +full:x1c00
16 #define SMX_APE_BASE 0x68000000
19 #define OMAP34XX_GPMC_BASE 0x6E000000
22 #define OMAP34XX_SMS_BASE 0x6C000000
25 #define OMAP34XX_SDRC_BASE 0x6D000000
30 #define OMAP34XX_CORE_L4_IO_BASE 0x48000000
31 #define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000
32 #define OMAP34XX_ID_L4_IO_BASE 0x4830A200
33 #define OMAP34XX_L4_PER 0x49000000
37 #define OMAP34XX_DMA4_BASE 0x48056000
40 #define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE + 0x2000)
45 unsigned char res[0x408];
46 unsigned int io2; /* 0x408 */
47 unsigned char res2[0x38];
48 unsigned int io0; /* 0x444 */
49 unsigned int io1; /* 0x448 */
54 #define PRG_I2C2_PULLUPRESX 0x00000001
57 #define OMAP34XX_SCRATCHPAD (OMAP34XX_CTRL_BASE + 0x910)
60 #define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE + 0x6a000)
61 #define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE + 0x6c000)
62 #define OMAP34XX_UART3 (OMAP34XX_L4_PER + 0x20000)
63 #define OMAP34XX_UART4 (OMAP34XX_L4_PER + 0x42000)
66 #define OMAP34XX_GPT1 0x48318000
67 #define OMAP34XX_GPT2 0x49032000
68 #define OMAP34XX_GPT3 0x49034000
69 #define OMAP34XX_GPT4 0x49036000
70 #define OMAP34XX_GPT5 0x49038000
71 #define OMAP34XX_GPT6 0x4903A000
72 #define OMAP34XX_GPT7 0x4903C000
73 #define OMAP34XX_GPT8 0x4903E000
74 #define OMAP34XX_GPT9 0x49040000
75 #define OMAP34XX_GPT10 0x48086000
76 #define OMAP34XX_GPT11 0x48088000
77 #define OMAP34XX_GPT12 0x48304000
80 #define WD1_BASE 0x4830C000
81 #define WD2_BASE 0x48314000
82 #define WD3_BASE 0x49030000
85 #define SYNC_32KTIMER_BASE 0x48320000
90 unsigned char res[0x10];
91 unsigned int s32k_cr; /* 0x10 */
94 #define DEVICE_TYPE_SHIFT 0x8
95 #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
101 unsigned char res1[0x34];
102 unsigned int oe; /* 0x34 */
103 unsigned int datain; /* 0x38 */
104 unsigned char res2[0x54];
105 unsigned int cleardataout; /* 0x90 */
106 unsigned int setdataout; /* 0x94 */
110 #define GPIO0 (0x1 << 0)
111 #define GPIO1 (0x1 << 1)
112 #define GPIO2 (0x1 << 2)
113 #define GPIO3 (0x1 << 3)
114 #define GPIO4 (0x1 << 4)
115 #define GPIO5 (0x1 << 5)
116 #define GPIO6 (0x1 << 6)
117 #define GPIO7 (0x1 << 7)
118 #define GPIO8 (0x1 << 8)
119 #define GPIO9 (0x1 << 9)
120 #define GPIO10 (0x1 << 10)
121 #define GPIO11 (0x1 << 11)
122 #define GPIO12 (0x1 << 12)
123 #define GPIO13 (0x1 << 13)
124 #define GPIO14 (0x1 << 14)
125 #define GPIO15 (0x1 << 15)
126 #define GPIO16 (0x1 << 16)
127 #define GPIO17 (0x1 << 17)
128 #define GPIO18 (0x1 << 18)
129 #define GPIO19 (0x1 << 19)
130 #define GPIO20 (0x1 << 20)
131 #define GPIO21 (0x1 << 21)
132 #define GPIO22 (0x1 << 22)
133 #define GPIO23 (0x1 << 23)
134 #define GPIO24 (0x1 << 24)
135 #define GPIO25 (0x1 << 25)
136 #define GPIO26 (0x1 << 26)
137 #define GPIO27 (0x1 << 27)
138 #define GPIO28 (0x1 << 28)
139 #define GPIO29 (0x1 << 29)
140 #define GPIO30 (0x1 << 30)
141 #define GPIO31 (0x1 << 31)
144 #define SRAM_OFFSET0 0x40000000
145 #define SRAM_OFFSET1 0x00200000
146 #define SRAM_OFFSET2 0x0000F800
151 #define NON_SECURE_SRAM_START 0x40208000 /* Works for GP & EMU */
152 #define NON_SECURE_SRAM_END 0x40210000
153 #define NON_SECURE_SRAM_IMG_END 0x4020F000
156 #define LOW_LEVEL_SRAM_STACK 0x4020FFFC
175 #define CPU_3430 0x3430
179 * ES1 = rev 0
185 #define CPU_3XX_ES10 0
195 * ES1.0 onwards, the value maps to contents of IDCODE register [31:28].
198 #define CPU_37XX_ES10 0
205 #define WIDTH_8BIT 0x0000
206 #define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */
211 #define HAWKEYE_OMAP34XX 0xb7ae
212 #define HAWKEYE_AM35XX 0xb868
213 #define HAWKEYE_OMAP36XX 0xb891
220 #define CPU_OMAP34XX 0x3400 /* OMAP34xx/OMAP35 devices */
221 #define CPU_AM35XX 0x3500 /* AM35xx devices */
222 #define CPU_OMAP36XX 0x3600 /* OMAP36xx devices */
227 #define OMAP3503 0x5c00
228 #define OMAP3515 0x1c00
229 #define OMAP3525 0x4c00
230 #define OMAP3530 0x0c00
232 #define AM3505 0x5c00
233 #define AM3517 0x1c00
235 #define OMAP3730 0x0c00
236 #define OMAP3725 0x4c00
237 #define AM3715 0x1c00
238 #define AM3703 0x5c00
240 #define OMAP3730_1GHZ 0x0e00
241 #define OMAP3725_1GHZ 0x4e00
242 #define AM3715_1GHZ 0x1e00
243 #define AM3703_1GHZ 0x5e00
265 #define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 26)
267 #define OMAP_REBOOT_REASON_OFFSET 0x04